Research On Key Technologies Of Flip-Flop Design Based On Sense-Amplifier

With the vigorous development of the human aerospace industry and integrated circuits,radiation-hardened electronic devices with high speed and low power consumption become more and more important.Sense-amplifier based flip flop has the characteristics of short setup time/hold time,low clock load,and is suitable for low-voltage and highspeed operation.Conventional SAFF has the disadvantage that output Q and inverted output QB depend on each other,so there are many improved SAFF designs,such as Nikolic SAFF,Ahmadi SAFF,Strollo SAFF,Kim SAFF,etc.However,the sensitivity of SAFF to Single Event Upset is not considered in these designs above.Due to the small voltage swing required for the differential input operation at the master stage of SAFF,its noise margin is smaller.SAFF is more susceptible to SEU,which could lock wrong logical values and even cause a system failure.If this happens in aerospace equipment,it will cause serious consequences.This dissertation proposes a cross-layer dual modular redundancy hardened scheme of SAFF,which can effectively improve the robustness of SAFF.That is,the unit level dual modular redundancy hardened technology is used at the master stage of SAFF,while the transistor level dual modular redundancy hardened technology is used at the slave stage.The proposed hardened scheme could be applied to the current typical SAFF designs,such as Con SAFF,Strollo SAFF,Ahmadi SAFF,Jeong SAFF,etc.The proposed crosslayer dual modular redundancy hardened scheme greatly improves the fault tolerance of SAFF.Hardened SAFF can not only fully tolerate single node upset of internal sensitive nodes,but also partially tolerate double node upset caused by charge sharing.Although the proposed cross-layer dual modular redundancy hardened scheme brings some loss of area and power consumption,compared with the traditional dual modular redundancy hardened scheme,the proposed hardened scheme still has a great improvement in delay,area,and power consumption.Detailed HSPICE simulation experiments and comparative data show that the proposed hardened scheme achieves a good compromise in terms of SEU tolerance,area,delay,and power consumption.This dissertation also proposes a novel flip flop design based on sense-amplifier,Cinv SAFF,which could further improve the performance of SAFF.Cinv SAFF adopts the master stage of Con SAFF and introduces a latch based on C element as its slave stage,which effectively simplifies the number of transistors and reduces the area and power consumption.The output inverter of Cinv SAFF isolates the output capacitive load from the internal structure and plays a role in shielding the internal noise and glitches.Detailed HSPICE simulation results show that the output waveform of Cinv SAFF is regular and glitch-free,and Cinv SAFF is suitable for high-speed operation and can work in the highfrequency environment of 2GHz.Compared with the existing SAFF,the power consumption,area overhead,and power delay product of Cinv SAFF are reduced by 24.77%,25.62%,and 19.3% on average without load.In a word,Cinv SAFF has good characteristics of power consumption,area overhead,and power delay product,and it is also comparable in terms of delay.