Research Of Radiation Hardened Circuit By Design In Nano-technology Integrated Circuit

With the development of integrated circuits process, the decreasing feature size, power supply and internal nodes capacitance make the traditional latch more susceptible to soft errors induced by radiation effects. The single event effect has two types. One is single event upset in sequential elements, and the other is single event transient in combinational logic circuit. When a particle hits sensitive node in combinational logic circuit, and the pulse may be latched by memory cells, which is called SET.When a particle hits internal nodes, if deposit charge produced by the particle is over the critical charge, there will be an upset, that’s called SEU. When a particle hits the internal nodes of the sequential element, if deposit charge produced by the particle is over the critical charge, there will be an upset, which is called SEU. On the one hand, SET pulse can be blocked by electrical masking, clock masking and logic masking in combinational logic circuit. On the other hand, recent experimental data indicate that the SEU is becoming more serious in radiation hardened by design in nanometer scale integrated circuit. As low cost error correcting codes have been used widely in high density memory cell, radiation hardened technology by design was more necessary in latch and flip-flop circuits. The main researches of this dissertation are the following:Firstly, we researched the single event effect caused by space radiation, and discussed its environment, mechanism of action, and effect on integrated circuit. In the meantime, we analyzed and classified the existing solutions for single event effect, and compared all the solutions with their advantages and disadvantages.Secondly, in order to enhance the reliability of traditional latch, a self-recovery soft error hardened latch (referred to as SRTL) suitable for low-power circuits is proposed. The proposed latch is based on transmission gate, feedback redundancy element and protection gates C-element. Feedback redundancy element include six nodes, each of node is driven by an NMOS and a PMOS transistor, which were connected to two different nodes. In 45nm technology we have compared our SEU tolerant latches with some proposed soft error tolerant latches. The simulation results trough comparisons with other hardened latches reveal that the proposed latch has the advantage of lower cost in terms of power, area, and delay.