The Key Technology Research Of Radiation Hardened High Speed QDR SRAM

QDR SRAM,as a new architecture memory with high speed and high bandwidth,greatly improves the performance of communication system.Core technology independently designing and mastering is of great importance to the development of memory domain and improvement of communication system performance.Based on the SMIC 65 nm process,this paper conducts key technology research on QDR SRAM including high-speed architecture design and radiation hardening.High-speed sequential read-write four-word burst architecture is proposed,and then a four-word burst architecture QDR II + SRAM circuit with 32 Mbit capacity is designed and implemented.The maximum operating frequency is up to 500 MHz,meeting the high-speed design requirements.And a creative RH-12 T memory cell structure that is resistant to single-event multi-node upset is proposed.Its anti-single-particle performance is superior to that of the DICE reinforced cell under the same design condition,providing a better memory cell solution for the anti-radiation performance of the circuit.Specific research contents are as follows:(1)After analyzing the timing of read and write operation of four-word burst architecture QDR II+ SRAM,two kinds of QDR II+ SRAM burst architectures,sequential read-write pipeline and concurrent read-write pipeline,are conceived and analyzed.Considering the timing constraints and circuit design complexity,sequential read-write pipeline four-word burst architecture is selected as the architecture of this paper.Followed by the realization of the overall structure of 32 Mbit QDR II+SRAM,reasonable read and write timing distribution program is proposed according to read and write wait cycle.(2)The control circuit module in the QDR II + SRAM four-word burst architecture proposed in this paper is designed to realize functions such as synchronous read and write instruction processing,independent read and write address sampling,byte write selection control and DDR data transmission.A read and write control circuit is proposed to realize the correct read and write function of QDR SRAM.At the same time,it can recognize the abnormal command request and prevent the circuit from reading and writing error.Combined with the DDR input data control module,the burst data word is written into IP by byte,and the byte write selection signal is added for chip selection to realize byte write selection control function of the write data.(3)A RH-12 T memory cell structure is proposed,it utilizes single-level sensitive island node storage technology by surrounding the output nodes with merely NMOS,which ensures a “0” storage node insensitive against energetic particles.At the same time,at least two nodes remain unchanged to restore the cell status through the feedback circuit when any single node is flipped,which result in single node upset immune characteristics.Base on cell layout design using the sensing node separation and SET reduction principle,single-particle flip simulation of three-dimensional physical model for RH-12 T cell provides that LET upset threshold of the proposed cell is 2.8 times that of the common DICE reinforced structure.