Research On Column-level ADC Applied To TOF Sensor

With the innovation and development of three-dimensional imaging technology,3D image sensors based on the Time of Flight(TOF)method have become a research hotspot in recent years due to the characteristics of high robustness,small size,and fast imaging speed..Analog to digital converter(Analog to Digital Converter,ADC)as the core module of TOF sensor,its performance is the key factor that determines the imaging quality and ranging accuracy of the sensor.Therefore,it is of great significance to study the analog-to-digital converter in this sensor.In this paper,through the research and analysis of the TOF sensor imaging and ranging mechanism,a column parallel analog-to-digital converter applied in the TOF sensor is designed.Combined with the actual application requirements and the analysis and comparison of several column parallel analog-to-digital converters,the ADC designed in this paper is implemented with a single-slope structure,and the accuracy is determined to be 11bit,the sampling rate is 66.67KSps,and the quantization range is 2.4?2.8V Design goals.The designed ADC is composed of ramp generator,comparator,counter,register and sequential circuit.In the design of the ramp generator,this paper uses internal self-calibration technology to effectively solve the impact of the slope generator slope offset on the system accuracy;in the design of the comparator,this paper uses single-stage pre-amplification and dynamic latch cascade,And adopts input offset cancellation technology,which saves power consumption and suppresses the impact of offset voltage on the system;the use of Gray code counting in the design of the counter effectively reduces the bit error phenomenon.The column parallel analog-to-digital converter used in the TOF sensor designed in this paper uses the East Korea Electronics 0.13?m 1P4M CMOS image sensor process to complete the circuit schematic and layout design,and simulation verification and analysis.The previous simulation results show that the DNL is-0.1LSB/+0.3LSB;the INL is OLSB/+1.6LSB;the ENOB is 10.96bit,the SNR is 68.3dB,and the SFDR is 78.2dB;the power consumption of the single-column comparator is 1.96?W.The post-simulation results show that the ENOB is 10.43bit,the SNR is 65dB,the SFDR is 74.8dB;the single-row comparator power consumption is 3.6?W.The area of the whole sensor chip is 5×5mm2,and the layout width of the single-row comparator is 5?m.The tape test results show that the designed ADC functions normally and has good linearity.The depth imaging function of the TOF sensor chip is normal.