Study Of Time Skew Calibration Technique For High Speed TIADC

The rapid development of modern communication systems put forward requirements of high-speed and high-precision on analog-to-digital converter.However,with the limitations of process,the performance of monolithic ADC has reached the physical limit,and time-interleaved ADC?TIADC?that parallelly samples with multiple ADCs is an effective way to achieve high speed and high precision.However,in actual production,it is affected by non-ideal factors such as process environment,which lead to mismatch between sub-channels of time-interleaved ADC and eventually decrease the dynamic performance of TIADC system.This thesis firstly introduced the research background and significance of high-speed TIADC,then analyzed the three main mismatches:offset mismatch,gain mismatch,time mismatch and their impact on TIADC system performance.For the most complicated timing mismatch of calibration,the calibration was performed by using the fully-digital background calibration algorithm and the digital-analog hybrid calibration method.The fully-digital calibration algorithm used the characteristics of the signal to estimate the correlation of timing mismatch,and the least mean square?LMS?algorithm is used to iteratively estimate the value of timing mismatch,the first order five-point method based on Taylor series expansion is used to compensate the timing mismatch.The proposed algorithm did not require a reference channel and had low hardware consumption,it also works for wide bandwidth inputsignal.The digital-to-analog hybrid calibration method used an fully-digital method to extract the timing mismatch and then the timing mismatch is compensated by using a variable delay line.In this thesis,based on the Matlab/Simulink platform,a timing mismatch calibration model of a 1GHz four-channel 8-bit TIADC was built.When the normalized frequency of the input signal is f_in/f_s=0.414,the simulation results showed that the effective number of bits?ENOB?increased from 5.58bit to 7.88bit,spurious free dynamic range?SFDR?increased from 38.64dB to 67.53dB;then the RTL level simulation of the fully-digital calibration algorithm was completed based on the Modelsim platform;then the code was downloaded to the FPGA development board by using the Quartus II software to complete the hardware simulation of the calibration algorithm;the process based on the SMIC the0.18um completed the ASIC design of the calibration algorithm.Finally,the verification results of the calibration algorithm on different platforms were compared and analyzed,and the effectiveness of proposed calibration algorithm was verified.In addition,this paper also used the digital-analog hybrid calibration method to calibrate the timing mismatch.After calibration,the ENOB increased from 7.20bit to 7.87bit,and the SFDR increased from 50.75dB to 67.53dB.