Research And Design Of A 14-bit SAR ADC

With the fast developments of IoT industries such as smart house,smart power grid,and industrial auto-control,analog-to-digital converter(ADC)is becoming more and more important as it behaves as a bridge between the physical world and the digital world.High precision,low power and low latency are appriciated for ADCs in such applications.The charge-redistribution successive Apporoximation Register(SAR)structure is a suitable choice in IoT applications for its prominent power efficiency and its main-body's attribute of digital circuits.Unlike other ADC structures,SAR ADC benefits from CMOS process progress,and the consumed power substantially drops when the sample rate reduces.Hence,SAR ADC has become a focus in both industrial field and academic field,recently.This dissertation studies the key techniques associated to the design of a high precision SAR ADC,and designs a 14 bit 1 MS/s synchronous SAR ADC with on-chip reference buffer in a 130 nm CMOS process.The charge-redistribution digital-to-analog converter(DAC)adopts a three-section structure and hence reduces the numbers of unit capacitor.Three redundant bits are added to calibrate the dynamic errors,relaxing the requirement in DAC settling.An improved self-calibration technique is proposed to correct mismatch errors.The attendant gain errors is corrected in background.The highest three bits of DAC are controlled by 7-bit thermometer code instead to reduce differential nonlinearity(DNL)errors.The preamplifiers in comparator store their off-sets at outputs and cancel them in comparison.Moreover,the thermometer code decoder is optimized in transistor level to minimize the gate delays.The designed digital calibration method is verified through introducing 3%mismatches in a set of unit capacitors.The whole ADC including reference buffer occupies 0.24 mm2,and consumes 5.352 mW in power.The post-simulation shows a worst ENOB of 13.2 and a worst SFDR of 89 dB across all corners and-40-80? temperature range.