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Study And Design Of High-Precision Successive Approximation Register Analog-to-digital Convert

Posted on:2021-11-12Degree:MasterType:Thesis
Country:ChinaCandidate:M ZhaoFull Text:PDF
GTID:2518306050454204Subject:Master of Engineering
Abstract/Summary:PDF Full Text Request
In recent years,technologies such as the integrated circuit industry and the Internet of Things have developed rapidly.As the conversion circuit of analog signals and digital signals,the demand for analog-to-digital converters is rapidly increasing.Among them,SAR ADC is widely used in various systems,such as portable medical devices,artificial intelligence,and autonomous driving,due to their comprehensive advantages of low power consumption,small area,moderate speed and accuracy.As a result,the accuracy requirements for SAR ADC have also increased.However,the capacitor mismatch error caused by the process reduces the linearity of the analog-to-digital converter,which greatly limits the improvement of the accuracy of the SAR ADC.Generally,without any calibration method,the accuracy of the SAR ADC can only be about 12 bits.Reducing the impact of capacitor mismatch errors is the focus and difficulty of achieving high-precision SAR ADC.Based on UMC 55 nm CMOS process,this thesis designs a high-precision SAR ADC with16 bit precision and 1MS/s speed.In order to reduce the impact of capacitor mismatch error and achieve high accuracy,this paper designs a digital calibration algorithm based on self-calibration,that is,the method of quantizing the high-order capacitance weight by the low-order capacitor to correct the capacitor's mismatch.At the same time,non-ideal factors such as noise,comparator offset voltage,and parasitic capacitance in the circuit will also affect the calibration effect of the calibration algorithm.In order to improve the stability of the calibration algorithm,the calibration algorithm uses a combination of forward and reverse switching techniques for the effect of the offset voltage of the comparator;for the impact of circuit noise,a low-capacitance repeated calibration technique is used;for the comparator error caused by long stabilization time of DAC,redundant design is added;finally,differential calibration technology is used to further enhance the stability of the calibration algorithm.After that,the calibration algorithm model was built through MATLAB,and the calibration algorithm was perfected and verified at the behavioral level.The simulation results show that the calibration algorithm in this paper can tolerate 1m V offset voltage,200?V noise voltage,and 15%capacitor mismatch error.And make the effective number of ADC increase from 7 bit to 14.5 bit or more.In order to ensure the accuracy of the ADC and the effectiveness of the calibration algorithm,the design of the ADC circuit section is also very important.The main research contents of the ADC's overall circuit architecture are:(1)A low-noise and high-precision comparator is designed.In order to reduce the equivalent input noise and improve the comparison speed,a two-stage preamplifier and Latch cascade structure is used.At the same time,the offset calibration technology is applied to calibrate the offset voltage of the comparator to improve the accuracy of the comparator.The simulation results show that the comparator has an equivalent input noise voltage of 20?V,can distinguish an input voltage of 10?V,and can calibrate an offset voltage of 2.3m V.(2)Research and design a digital-to-analog converter(DAC)with redundant differential structure.In order to increase the size of the unit capacitor,a segmented capacitor structure is used,which is divided into high 11 bits and low 10 bits,and the unit capacitance is increased to 12 f F,the total capacitance of the single-ended DAC is 9.7p F.(3)The digital logic control part,including the calibration algorithm logic and the SAR logic during normal conversion,was researched,designed and optimized.Finally,in this paper,the overall SAR ADC is subjected to layout drawing and post-simulation verification.The layout area is about 600?m * 660?m.The simulation results show that at a speed of 1MS/s and a capacitor mismatch error of 10% the calibration algorithm can make the ENOB of ADC increased from 7.36 bit to 14.72 bit,SNDR increased from 46.11 dB to 90.38 dB,SFDR increased from 49.62 dB to 102.56 dB,and the average power consumption was 8.7mW.
Keywords/Search Tags:Digital Calibration, Self-Calibration, High-Precision, SAR, ADC
PDF Full Text Request
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