A 16-bit Adc Design

A 16 bit successive approximation Analog to Digital Converter is presented in this paper, based on a capacitor array charge redistribution technology. With the rapid development of computer, signal process and micro-electronic technology, new and advanced electron system comes forth largely. In the past twenty years, digital IC development improves signal process ability. This systems are be used for continuous time signal, including video, voice, medicine imaging, radar, instrument, consumed electrical appliance, and long-distance communication so on. Their successful use attribute to the rapid development of ADC (It can convert continuous signal to digital signal, which is discrete and binary system .At the same time, the output of ADC is convenient for accurate and high speed digital signal process).Most capacitor-based successive-approximation analog-to-digital A/D converters used in high resolution applications also require a large total capacitance, which in addition to a large die area; hence the speed of the operation is also substantially limited. But the architecture of the charge redistribution D/A converter with divider capacitor array presented in this paper can greatly release the area cost. In this paper, the use of a binary weighted capacitor array to perform a 16-bit successive approximation conversion is discussed. This paper concludes the principle and implementation of SAR A/D converter. All the designs including analog, logic and layout were completed by custom in a top-down flow. Main efforts were made here on the design details of charge redistribution D/A, low offset voltage comparator and error calibration circuits. How to minimize the disturbance of noise in mixed signal circuits and effects of nonideal circuit quality are two important problems in designing a desired A/D converter. So great efforts were made to release these disturbances during the design of offset cancellation of the analog comparator and mismatch reduction of the capacitor arrays. A monolithic prototype successive approximation A/D converter based on the described architecture was implemented using a 0.6um-DPTM standard Bi-CMOS process. A resolution of 16 bits was achieved with a conversion time of 5us. The chip, including all digital logic and output buffer dissipates 100mW with a 5-V power supply and 200KHz clock. In Chapter 2, a description of some terms and performance metrics of A/D converter was presented. A comparison of several architecture A/D converter is also given. In Chapter 3 of this paper, the principle of SAR AD converter and the operation of charge redistribution DA converter were described in this chapter, too. In Chapter 4, the design and simulation of the block circuits used in this SAR AD converter were presented. The layout effect on the circuit performance and how to design the layout to release the effect were given in Chapter 5. Chapter 6 summarized this paper.