125 Ksps Successive Approximation Adc Design

A10-bit125Ksps R-C hybrid structure SAR ADC IP fabricated in a65nm CMOS process is studied and developed in this thesis.6-bit charge-redistribution DAC is taken for the first6MSBs and4-bit R-DAC for the left4LSBs to reach low power consumption and small area. Binary to Thermometer encoding is involved in the fist4MSBs for good monotonicity and linearity. Another set of switches and offset cancellation timing are used for R-DAC to calibrate whole ADC’s DC offset. A pre-set timing for decision-register could save a half cycle of master clock for whole conversion cycle and only have a data latency of10.5-cycles. For kick-back noise suppressing, the control timing is used in comparator design to separate pre-amplifier and dynamic latch. Boosting function is used to prevent attenuation at input of dynamic latch.The ADC is tested. The circuit is operating on mix power supplies,2.5V for analog and1.2V for digital,3V is used for I/O. Test result shows DNL is+/-0.3LSB, INL is+/-0.55LSB, ENOB is9bit, and THD-60.01dB. The ADC IP occupies an area of0.036mm2. Total power consumption is500uW with a FOM of3.9pJ/conv.-step.