Design And Verification Of Digital Oversampling CDR

In the field of high-speed data transmission,the clock data recovery circuit at the receiving end is a core module in the entire data transmission system,which is to recover the received data without a clock signal correctly.However,during the transmission process,the data is influenced by the non-ideal transmission medium.The receiving end often receives the distorted data,and when the rate of data transmission increases,the influence of the external transmission medium is stronger,and the distortion of data is more serious.Then,it is necessary to design a CDR circuit with high performance.The research of this thesis is the digital oversampling CDR,and it focus on two aspects: the design and the verification.In terms of design,It investigated the current development of the clock data recovery circuit,which included the basic principles of clock data recovery technology,several common clock data recovery circuit structures,and their advantages and shortages,considering the less dependence on the circuit process and low sensitivity,I determined that the design used an oversampled digital CDR,finally.During the design process,a shaping filter unit is added to the original oversampling clock data recovery circuit to remove the influence of the jitter glitch of the input data.Finally,the entire design includes an CDR module to recovering data and SP module for data bit conversion,where the CDR module is further composed of a sampling synchronization unit,a shaping filtering unit,an edge detection unit,and a data recovery unit.In order to increase the operating frequency of the entire system,the entire design uses a pipeline structure.In order to get the best performance,two schemes of sampling synchronization module are designed: buffer synchronization and register direct synchronization.And two schemes of data recovery module also are designed: improved intermediate sampling recovery and phase-detection coding recovery.By comparing the timing results,power consumptions and area results of using different design schemes which are got by using Design Compiler based on the SMIC 40 nm process,it get the final design,which is: the sampling synchronization module uses register direct synchronization and the data recovery module uses improved intermediate sampling recovery are determined.The result of Design Compiler indicate system frequency can reach 2GHz.In terms of verification,it uses UVM verification methodology to build the verification platform.Firstly,it has analyzed the common architecture and main components of the UVM verification platform.Besides,it has researched the common verification mechanisms of UVM.Then,it has made the current design as the verification object,and completed the construction of the verification platform.Based on the verification plan,the following has been completed: analysis of verification content,verification function point extraction,verification platform construction,test case writing and coverage check.By analyzing the characteristics of the currently designed CDR circuit,it has designed the corresponding test cases,the simulation environment is that the under recovered data with the data rate and system clock has 1% frequency difference,the jitter glitch length accounts for 10% of the signal,the input data use 8b/10 b encoding and Manchester encoding respectively.Finally,all test cases were passed,and the function coverage and code coverage are 100% and 99.71% respectively.The verification results show that the currently designed CDR circuit can correctly recover the input data with edge glitch without error,and it gets all features that it requires.