Research And Design Of High Performance Oversampling CDRs

The clock and data recovery circuit is a basic module in many wired high-speed datatransmission systems. The circuit is used to recover the clock and data from the distortion of datacorrectly. Due to the non-ideal transmission medium, such as limited bandwidth and non-uniformgroup delay or external crosstalk and noise, the datas are often seriously distorted in the receiver.So in order to minimize the error rate, and recover the clock and data high-qualitily, it requiresCDRs have high performance and reliability.This paper summarizes the structure of general blind oversampling clock and data recoverycircuit and compares several typical data recovery logic, what’s more, analyzes their advantagesand disadvantages. According to my design, chosing the phase encoding method, and then addinga sync adjustment circuit, a filtering and shaping circuit to improve the performance of the design.Then doing researchs for the semi-blind oversampling clock and data recovery circuits, andexplaining the relationship between blind oversampling clock and data recovery circuit andsemi-blind oversampling clock and data recovery circuits. This circuit will add a frequencydetector in front of general semi-blind oversampling clock and data recovery circuit throughcomparison and improvement to constitute bicyclic structure, it will lock sampling clock bycoarse and fine adjustments. This paper also describes the important module DACs and VCOs indetail.Blind oversampling clock and data recovery circuit will be verified by the low-cost FPGAprogrammable devices, the highest rate of recoveried data can be200Mbps. The proposedfiltering and shaping circuit can effectively improve the sampling data stream, so that, the circuithas greater ability to suppress noise and interference. The basic principles of the semi-blindoversampling clock and data recovery circuit is studied in this paper, the circuit use all-digital anddigital-analog hybrid design method, the BER of CDRs will be lower through improvements, thephase locking time will also be shorter. The recovered data sequence by CDRs can be1.25-4Gbps,the locking time is2.6μs.