Study Of Design And FPGA Implementation Of 5G-LDPC Codec

In a digital communication system,channel coding is a key technique in physical layer,where LDPC code as one of the best error correcting code,has been shown to be the most close to the capacity limit error correction code.In November 2016,through in-depth discussions,LDPC code has been chosen as data channel coding scheme of the e MBB scenario for 5G mobile communications system in 3GPP RAN1 87 meetings.In the face of more diversity application scenarios and higher technical index for 5G communications,it urgently needs a more flexible,faster and more efficient encoder and decoder implementation.In view of the LDPC code,this thesis has completed hardware architecture design and FPGA implementation of the encoder and decoder based on the 5G NR standard,which can be compatible with a complete set of 5G LDPC codes.In terms of the encoder,according to the structure characteristics of check matrix of 5G LDPC codes,combining with the common coding algorithm of single diagonal check matrix coding method and double diagonal check matrix coding method,this thesis has designed a kind of double diagonal add single diagonal check matrix coding method for 5G LDPC codes.The main calculation operations in the encoder are realized by cyclic shift network and simple XOR logic.According to the presence of related parameters in the ROM,the designed encoder can realize the online dynamic configuration and implement a set of encoder compatible with a complete set of 5G LDPC codes.Based on Xilinx ZYNQ-7 ZC706 evaluation board(xc7z045ffg900 chip)development platform,the design simulation and on-chip implementation have been done: Through the optimization design,the encoder can work well at a clock frequency of 200 MHZ;under the condition of low on-chip resource consumption(5.17% LUT consumption and 2.02% FF consumption),the highest throughput rate of the designed encoder can be up to 20.365 Gbps.In terms of decoder,since the companies such as Qualcomm,Ericsson,Samsung,ZTE propose a layered parallel structure,this thesis has chosen layered min-sum algorithm(MSA).Considering the two different decoder implementation architecture-line parallel and block parallel,this thesis has completed on FPGA implementation of decoder compatible with a complete set of 5G LDPC codes.The main computation in the decoder can be implemented by simple adders and subtracter,cyclic shift network,muxers and comparators,the designed decoder can dynamically configure at work according to the external input parameters,which makes a set of compatible hardware decoder compatible with a complete set of 5G LDPC codes.Based on Xilinx ZYNQ-7 ZC706 evaluation board(xc7z045ffg900 chip)hardware platform,the decoder with a block parallel architecture can work well at a clock frequency of 150 MHZ,where the LUT consumes 5.59%,the FF consumes 2.28%,and its highest throughput rate is 124.4 Mbps.The decoder with line parallel architecture can work well at highest working frequency of 120 MHZ,where the LUT consumes 62.5%,the FF consumes 10.66%,and the highest throughput rate is 1.584 Gbps.At the same time,aiming at the message passing limitations of layered decoding algorithm in hardware implementation,this thesis proposes a pipeline decoding strategy between frames,which can effectively improve the work efficiency of the decoder cell,information updated clock cost of each layer can be reduced to one clock cycle.Using this strategy,theoretical throughput rate of the designed decoder can reach more than 30 Gbps.