The Implementation On Algorithmic And FPGA Of Digital Terrestrial Multimedia Broadcasting On Low-Density Parity-Check Codes

Error-correcting codes are widely used in many fields,such as mobile communication,satellite communication,and so on.Low-Density Parity codes (LDPC),one kind of Error-correction codes,is defined in terms of very sparse matrices,and can be decoded by iteration algorithms.It was first investigated in 1962 by Gallager,but appear to have been largely forgotten.Mackey and Wiberg rediscovered their excellent property of achieving information rates up to the Shannon limit,after the extreme success of Turbo codes.In this thesis,several iterative message passing algorithms for LDPC codes of DTMB,such as Sum Product Algorithm, Min Sum Algorithm, Layered Revised Min Sum Algorithm etc,are considered.At the same time,some key parameters and finite precision analysis for the hardware implementation of LDPC decoder have been performed considering the tradeoff between hardware complexity and error performance.Eventually,the architectures for the hardware implementation of LDPC decoder,including full parallel architecture,partly parallel architecture and serial architecture,have been analyzed. it is difficult to implement by partly parallel architecture as the the randomness distribution of the checking matrix. And the check matrix in DTMB is too large, full-parallel structure is clearly not applicable.This paper, a hardware implementation method based on serial architecture is introduced.This method can not only reduce hardware decoder complexity, but also close to the random construction LDPC code performance.To demonstrate this design methodology, An irregular LDPC decoder with a code length of 7493 bits and the rate of 0.4 0.6 0.8 for DTMB system was implemented with the device of Xilinx's Virtex-4 family XC4VLX200.The design is described in the Verilog hardware description language(HDL).By performing maximum 31 decoding iterations and with the decoder clock frequency of 120MHz.