FPGA Implementation Of High Speed LDPC Codes Encoder And Decoder Based On DVB-S2

With the LDPC codes have chosen as the coding scheme of the data channel in the scenario of enhanced mobile bandwidth in the fifth-generation mobile communication system(5G),as well as the research work carried out on the requirements and technology of the new generation of mobile communication(6G),fully demonstrates that whether it is in the design of future air-space-ground integration coding scheme design work,or for the rapid advancement of the current 5G market,it is inseparable from the excellent performance of LDPC codes as a channel coding scheme.Aiming at the satellite communication DVBS2 standard,the code structure using the cascade of LDPC codes and BCH codes has a performance close to the Shannon limit,but with the continuous development of satellite communication,in the process of data transmission,there is an urgent need for an LDPC codes encoder and decoder with lower delay and higher throughput to meet the needs of larger transmission data volumes,higher transmission rate and lower transmission delay.Based on the research background of satellite communications,this article focuses on the LDPC codes in the DVB-S2 standard and the research is carried out from theoretical analysis,algorithm simulation,and hardware implementation.It is based on Xilinx's xc7z100ffg900-2 FPGA chip and using Vivado as the development platform,Using Verilog hardware description language,finally the hardware implementation of high-speed LDPC codes encoder and decoder compatible with the DVB-S2 standard with a code length of64800 and a code rate of 1/2,3/4,and 8/9 is completed.In terms of the encoder,firstly,according to the check matrix of LDPC codes defined by the standard,a simplified encoding method based on a double diagonal structure is proposed.From the perspective of hardware implementation,by introducing iterative intermediate variables to simplify the core encoding process of LDPC codes,thereby reducing the use of hardware resources and reducing the dynamic power consumption of the encoder;Then,optimizes the storage method of iterative intermediate variables through the use of distributed storage,it is compatible with multiple code rates while reducing the consumption of hardware storage resources;The finally designed LDPC encoder can work stably at a clock frequency of 200 MHz,and can realize dynamic switching of multiple code rates.In the case of low hardware resource usage(LUT utilization 1.55%,FF utilization 0.91%),the encoder throughput rate is 200 Mbps.In terms of the decoder,firstly,the initial structure of LDPC codes check matrix defined by the standard is improved.By transforming the initial check matrix to have a quasi-cyclic structure to improve the parallelism of the decoder,and considering the resource consumption of the decoder hardware implementation,a hardware architecture with a parallelism of60 is finally selected;Then,according to the normalized min-sum algorithm based on the hierarchical structure,a design method with a pipeline structure is proposed.While basically not affecting the decoding performance,it further reduces the delay of the decoding iteration and effectively improves the decoding rate and throughput of the decoder;The finally designed LDPC decoder can work stably at a clock frequency of up to 150 MHz.According to the external dynamic input global parameters,the decoder can adjust the supported code rate,the calculated bit width and the maximum number of iterations and other parameters.Under the condition of using hardware resources(LUT utilization 11.55%,FF utilization4.77%),the decoder can reach a throughput rate of 100 Mbps.