Research On Construction, Parallel Concatenation And Decoder Design Of Low-Density Parity-Check Codes

Low-density parity-check (LDPC) codes are excellent error-correcting codes with performance close to the Shannon limit, widely applied in many fields, such as wireless communication, satellite communication, digital broadcasting and magnetic recorders. This dissertation explores the applications of LDPC codes in beyond 3G (B3G) systems and communications based train control (CBTC) system. To address challenges of error floors, encoding and decoding complexity and hardware complexity, the construction, parallel concatenation and decoder design of LDPC codes are investigated.Chapter 3 presents two construction methods of LDPC codes with low error floors, called progressive edge-growth construction based on polynomial of cycle (PEGP) and progressive edge-growth construction based on weighed polynomial of cycle (PEGWP). With the aid of polynomial of cycle, PEGP construction maximizes the girth and minimizes the number of short cycles. Besides, PEGWP construction avoids short cycles passing through variable nodes with low degree. Simulation results show that PEGP and PEGWP constructions improve the performance and lower error floors of LDPC codes significantly.In chapter 4, a novel construction method for LDPC codes with fast encoding is proposed. An approximate lower triangular check matrix is constructed by modified PEGP method. Simulation results show that the constructed codes have linear encoding complexity and don't need performing row and column permutations before encoding with little performance degradation.In chapter 5, a new class of parallel concatenated codes built from LDPC codes, called parallel interleaved concatenated LDPC (PIC-LDPC) codes is introduced. PIC-LDPC codes break the fairly decoding complexity of long code into those of several shorter codes, while maintaining the information exchange between them. In this scheme, PIC-LDPC codes can achieve good performance with lower decoding complexity and reduced memory requirements.Chapter 6 discusses the design and implementation of LDPC and PIC-LDPC decoders. Two modified schedules, the schedule based on updating groups and the schedule based on distributed checks, are proposed. Simulation results show that the two schedules can enhance the throughput of decoder and improve the performance. The proposed decoder can achieve medium to high throughput using low-cost FPGA device.