FPGA Decoder Implementation For Quasi-Cyclic Low-Density Parity-Check Codes

First proposed by Gallager in 1962 and rediscovered in mid 1990s, Low-Density Parity-Check Codes became an important topic in error-correcting codes, because of its outstanding performance and great application potential. There have been many research breakthroughs in code construction, decoding algorithms, and engineering realization.This thesis aims at implementing an LDPC decoder in single FPGA, for Chinese Digital TV Terrestrial Broadcasting standard (GB20600-2006). The main research works we did are as following:Simulate and analyze several low complexity iterative LDPC decoding algorithms. We found modified min-sum algorithms can tremendously reduce the computational complexity, while keeping the performance degradation less than 0.2dB. We choose normalized min-sum algorithm as our decoding algorithm for implementation. To obtain an optimal performance-complexity trade off, we fix some key parameters by simulation, including normalization factor, maximum iteration number and quantization bits, which are essential to the error-correcting performance.Implement a semi-parallel decoder in single FPGA, by utilizing the quasi-cyclic property of the parity-check matrix. Semi-parallel architecture allows us to have a better trade off between resource usage and decoding throughput, and the quasicyclic parity-check matrix can greatly simplify the design and implementation of semi-parallel decoder. Moreover, normalized min-sum algorithm guarantees excellent performance with much less resource usage. Our LDPC decoder has been verified by lab test and field test of digital TV terrestrial broadcasting.