Design And Implementation Of Decoder For Quasi-Cyclic Low-Density Parity-Check Codes

The design and implementation of the encoder and decoder for Low-Density Parity-Check (LDPC) codes on FPGA device is studied by theoretical analysis and simulation. The main results and contents are as follows.1. The definition and structure of Quasi-Cyclic (QC) LDPC codes are introduced, the characteristics of the QC-LDPC codes in DTMB system are concluded.2. The linear time encoding problem for LDPC codes specified by parity-check matrix is studied. The issue of efficient encoding of QC-LDPC codes using simple shift registers is addressed. Based on this, the implementation design for encoder of QC-LDPC codes in DTMB system is proposed.3. The belief-propagation (BP) decoding algorithm for LDPC codes is presented. Four BP-based decoding algorithms and three kinds of information passing mode are summarized and compared systematically.4. Two partially-parallel decoder architectures for QC-LDPC codes are proposed. Based on the more efficient one a decoder for the three kinds of QC-LDPC codes in DTMB system is implemented on the FPGA device ALTERA StratixII-EP2S90F1020C5.