FPGA Implementation For Encoder And Decoder Of Quasi-Cyclic Low-Density Parity-Check Codes

Low density parity-check (LDPC) code was proposed in 1962 by Gallager, which is a kind of linear block codes based on a sparse check matrix. its decoding performance can achieve Shannon Limit. Many communication standards have already adopted LDPC codes as the Error-Correcting codes. So, the hardware implementation of LDPC encoder and decoder are one of the research interests at present.The main problem of LDPC encoding is to find an efficient encoding algorithm with linear complexity, and the main problem of LDPC decoding is to make a trade-off between hardware complexity, performance and throughput.QC-LDPC code is an important subclass of LDPC codes. Because of the cyclic symmetry, the encoding complexity of QC-LDPC codes are linearly proportional with code length and the decoding storage space is reduced greatly. This thesis studies both the theory and hardware implementation of LDPC codes, and implements the encoder and decoder of QC-LDPC codes on FPGA. The main works are as follows:1. The algorithm from the parity-check matrix to the generator matrix is realized when the check matrix is full rank, and the case when the check matrix is not full rank is also researched.2. Three fast encoding algorithms for QC-LDPC codes are researched and realized, which are serial encoder, parallel encoder and two-stage encoder. Based on the two-stage encoder, a more effective encoding structure by reusing the first stage circuits is proposed. Simulation results show that the encoding efficiency and working frequency are improved.3. Floating simulation of the LDPC encoding and decoding system is performed and fixed simulation of the Mim-Sum decoder is completed. The results show that there are about 0.3 to 0.5 performances losses and the fixed-point processing program is reasonable and effective.4. Hardware design and implementation of partially-parallel decoder are completed on the ISE 8.2 and modelsim 6.2 software platform using Verilog HDL.