Research And Implementation Of LDPC Codes Decoder

Since their excellent error-correcting capability and efficient decoding algorithm, low-density parity-check (LDPC) codes have received much attention and have been widely considered as next-generation error-correcting codes for many real-world applications, e.g., telecommunications and magnetic storage. Except for their excellent error-correcting capability, another important reason why LDPC codes attract so much attention is that Belief Propagation decoding algorithm is inherently fully parallelizable, and the computation associated with each node is very simple. Because of the excellent error-correcting capability and inherently fully parallelizability of LDPC codes, this thesis focused on their coding and decoding algorithm and the decoder hard ware implementation.First, there kinds of LDPC codes decoding algorithms have been analyzed, which are Gallager hard decision decoding algorithm, Gallager soft decision decoding algorithm and belief propagation decoding algorithm. It is provided the detailed deduction and demonstration of the Gallager soft and hard decision decoding algorithm. Further more it is provided the simulation results and performance analyses on the belief propagation decoding algorithm with different code lengths and iterations and an efficient coding algorithm-Efficient coding algorithm has been introduced.Second, the hard ware oriented (3, k)-regular LDPC code construction methord and the corresponding decoder architecture have been researched. A joint (3, k)-regular LDPC code and decoder/encoder design technique invented by Dr. Tong Zhang has been introduced. A detail description and discussion of the code construction processing, the principle of code choosing, code and decoding method, and the architecture of decoder have been given under the joint (3, k)-regular LDPC code and decoder/encoder technique.Finally, the implementation of partly parallel LDPC decoder on FPGA has been researched and realized a (3, k)-regular LDPC decoder with 4608 code length in StratixII EP1S25 FPGA. An improved method of the data input and output of the decoder has been presented, which need smaller storage space and the data input can complete in L clock cycles on the same decoder clock frequency. The realized decoder can achieve 96Mbps symbol through output on the condition of 20 iterations and the decoder clock frequency is 65MHz, while the bit error rate is 1.7×10?5at 2dB SNR over AWGN channel.