Research On Key Techniques Of High Speed Four Channel Time Interleaved Hybrid Structure ADC

The world of communication has evolved rapidly.Almost 10 years is an era.From 2G in the 1990s to 4G in 2010,mobile wireless networks are moving towards the era of 5G communication.5G networks require extremely high speeds,extremely large capacities and extremely low latency.These requirements place higher demands on analog-to-digital converters in electronic systems in the communications field,namely high precision,high speed and low power.Due to its structural characteristics,Pipelined ADCs can implement high-precision,high-speed ADCs,but because they contain a large number of op amps and comparators,power consumption increases with accuracy.SAR ADCs are superior to Pipeline ADCs in terms of energy efficiency.The advantages of SAR ADC are simple in structure and compatible with processes.However,since the principle of SAR ADCs is based on the successive approximation search algorithm,the speed is limited by the comparison speed and comparison times of the comparator,and it is difficult to meet the design requirements of the current high speed ADC.Based on the characteristics of the above two ADCs,Pipelined SAR ADC structure is proposed.However,the Pipelined SAR ADC is slower than the Pipeline ADC.To compensate for the speed problem,multi-channel time interleaving can be used.However,multi-channel time interleaving introduces timing,gain and offset mismatches.For the offset mismatch and gain mismatch between channels,a new PN code calibration technique is proposed in this thesis.In this thesis,the operational principle and architecture of the Pipelined SAR ADC are discussed briefly with a focus on the study of the multiplying digital-to-analog converter?MDAC?circuit based on traditional operational amplifier.Furthermore,a new type of residual amplifier circuit that multiplexes the comparator in the first-stage SAR ADC into a dynamic operational amplifier?RCAMP?structure is proposed.The overall power consumption,area and design complexity of the overall ADC are reduced.A randomized channel calibration technique based on pseudo-random code?PN?is also introduced.On the basis of the required four-channel time domain interleaving,an additional channel is added to achieve random selection of the channel.The channel can be completely randomized to eliminate the offset error and gain error caused by multi-channel time domain interleaving,and improve the spurious-free dynamic range?SFDR?of the overall ADC.Finally,a 12-bit 100MHz Pipelined SAR ADC is fabricated in TSMC 65nm 1.2V CMOS process.The overall effective area is 0.17mm² and the total power consumption is2.12mW.Furthermore,a 12-bit 400MHz time-interleaved Pipelined SAR ADC is faricated in TSMC 65nm 1.2V CMOS process.The overall effective area is 1.05mm² and the total power consumption is 7.16mW.The post-layout simulation results show that the single-channel ADC achieves 79.3dB SFDR,66.3dB SNDR and 10.71bit ENOB with Nyquist input at 100MS/s and the swing amplitude of 2.4V_PP.A test platform is built to evaluate the performance of the chip.The measurement results show that the ADC achieves 70.4dB SFDR,60.3dB SNDR and9.72bit ENOB with the Nyquist input at 10MS/s.It turns to 57.3dB SFDR,49.4dB SFDR with Nyquist input at 75MS/s.The DNL is within+0.91LSB/-0.79LSB and the INL is within+0.73LSB/-1LSB.The simulation results of four-channel time interleaved Pipelined SAR ADC improves 6.8dB SFDR with the Nyquist input at 400MS/s.