Realization And FPGA Verification Of Time Domain Expansion Compensation Algorithm For Pipelined Analog - To - Digital Converter

The speed and precision on signal processing have a great improvement because of the development of integrate circuits in these years. As the bridge between analog signal and digital signal, the analog to digital convertor and digital to analog convertor need to be improved in speed and resolution to keep the quality of signal in sampling, transmitting and other processes.Pipeline analog to digital convertor has moderate speed and moderate resolution. In these years, the speed and resolution of pipeline analog to digital convertor have been improved a lot. But it is hard to realize high speed and high resolution pipeline ADC in low power just with the intrinsic characters of devices because of the technology limitation. So researchers calibrate the errors caused by the limit of technology to improve the performance of pipeline ADC in different ways.Time-expanding calibration is a method to calibrate the errors caused by the capacitance mismatch and the limitation gain of operational amplifier. In this calibration a pseudorandom signal is added to the input signal. The pseudorandom signal will be processed with the capacitance mismatch and OPT limit gain. Making use of the characters of the pseudorandom signal, the message of errors can be abstracted from the output signal. A more precise result can be got after subtracting the pseudorandom signal and calibrating the errors from the output signal.The major work of the thesis is realizing the Time-expanding calibration and verifying it in FPGA. Firstly the architecture of the calibration circuit was designed. Then the circuit was described in Verilog language. The function of calibration circuit witch was described in Verilog can be verified through comparing the calibration code simulation result in Modelsim with the result in Matlab. Then the calibration circuit code in Verilog was downloaded to FPGA after its function was verified. The function of calibration circuit in FPGA can be verified by comparing the working result of calibration circuit in FPGA with that in Modelsim. Lastly the Verilog code of Time-expanding calibration circuit was synthesized in130nm CMOS technology. The calibration circuit area is0.7937mm2and power consumed is10.221mW when its work frequency is80MHz.At the end of thesis, a summary was made, testing the calibration in pipeline ADC and optimizing the calibration circuit was proposed in the next step.