A New Type Of Pseudo-pipelined Time - Digital Converter System Modeling And Research Of Key Technologies

The cellular phone industry continues to thrive with the combination of wireless commnication and multimedia functions. And the demand for low cost of the solutions brings the trend of integrating all radio onto a single die. The use of low-voltage deep-submicron CMOS processes allows for an unprecedented degree of scaling and integration in digital circuitry, but complicates implementation of traditional RF circuits, which is essential to the wireless communication circuitry. In order to resolve the conflict of digital design and RF design, all digital design of RF circuits is emerging as an epoch-making solution.All-digital PLL serves as the most important part of the all-digital RF circuits, with the advantages of preseting, restoring and recoverying of the internal state except for the fine nature of easy integration with digital circuitry. Besides, it can modulate the frequency directly through the "feedthrough" mode. The characteristics, including high controllability, good programmability, easy adjustability, and fine expansibility present the advantages of digital circuitry, and shift the RF function to digital circuitry.As the core module of all-digital PLL, time-to-digital converter determines its performance largely. Among the performance matrix, resolution of time-to-digital converter attracts the most attention, together with linearity and dynamic range. In the last two decades, the resolution of time-to-digital converter evolved from nearly a nanosecond to several picoseconds. However, the further improvement of the all-digital PLL still demands for its advancing to several femtoseconds. Accordingly, high-linearity high-resolution time-to-digital converter has become the most hot spot research issue.This paper analyzed and summarized most kinds of time-to-digital converter according to its developing history and presents the systematic structure and critical modules of a high-resolution pseudo-pipelined time-to-digital converter. System simulation results shows the proposed time-to-digital structure can eliminate the nonlinearity caused by the edge comparator largely, hence reduces the resolution limiting factors to one, the mismatch of delay elements. Meanwhile, this paper presents a closed-loop time-amplifier, which adds the feedback mechanic to the traditional open-loop one in order to stabilize its gain and provides sufficient evidence to the feasibility of the pseudo-pipelined time-to-digital converter. Moreover, this paper also presents the design of increasing the linear range of time-amplifier, which eases the tradeoff between the gain and the linear range of time-amplifier and offers the reference for designs using large scale manufacturing process. Finally, the paper illustrates the detailed structure of the sub-time-to-digital converter in each stage.