Research And Key Circuits Design Of Multi-channel High-speed Pipelined ADC

Analog-to-Dgital Converter (ADC) is an important part of system on a chip(SOC), and the rapid development of modern wireless communication technologyhas urgently demand for high performance ADCs. With the CMOS process widthdeveloping into the scope of submicron, deep submicron and nanometer, the designof high performance ADCs is challenged by nonideal factors brought about byscaling down of technology and low supply voltage, etc. Nowadays, theperformance of single channel ADC approaches to the technology limitations onspeed and accuracy in the present conditions. Time-interleaved technology can beapplied to make multiple single channel ADCs constitute a multi-channel system,effectively improving the sampling rate, ensuring the realization of high precisionand breaking through the technology limitations of single channel ADC. Offsetmismatch, gain mismatch, and timing skew mismatch among channels ofmulti-channel time-interleaved ADC (TIADC), however, seriously deteriorateperformance of TIADC.This thesis discusses the structure and principle of multi-channel TIADC, andanalyzes the detrimental effect on dynamic performance of TIADC resulted fromthe mismatches. On the base of these, a background calibration algorithm isimplemented for double-channel TIADC with reference channel. This algorithmeliminates the mismatches between channels with digital post-processingtechniques, and to guarantee effective calibration when input frequency of TIADCis high, a compensation scheme for correction of high-order timing skew errors isemployed. It is based on least-mean-square iteration which has advantages of lowcomputational complexity and easy in complementation. The single channelpipelined ADC and the double-channel TIADC with the reference are modeled byMATLAB programming language. Based on Chartered0.18μm CMOS technologyand the1.8V supply voltage, the circuits of the12-bit160MHz pipelined ADC and320MHz double-channel TIADC with the reference channel are designed bySpectre. By system-level, behavior-level and circuit-level verification, thecorrectness and the practicability of the TIADC calibration are done.Simulation results of circuit-level verification show that, with4%full scalerange offset mismatch,3%gain mismatch and1%sampling period timing skew mismatch, the sampling rate320MHz, when input frequency of the TIADC is12.96875MHz, signal to noise and distortion rate (SNDR) and spurious freedynamic range (SFDR) improve about64dB and48dB, achieve72.77dB and92.64dB, effective number of bits (ENOB) achieves11.8bits, and when inputfrequency of the TIADC is155.78125MHz, SNDR and SFDR improve about39dBand41dB, achieve66.21dB and67.19dB, ENOB achieves10.7bits.