Research And Design For Multi-Channel Time-Interleaved Pipelined ADC

High-speed ADC has wide applications in high-speed image and video processing,wireless communications, digital oscilloscope and other fields. With the increase of speedof these instrumentations, the conversion rate of the ADC used in them is required higher.However, the performance of single channel ADC is approaching technology limitationson speed and accuracy with conditions of the time.In order to improve the speed of ADC, time-interleaved architecture can be appliedon the design of ADC. However, offset mismatch, gain mismatch and sample-time erroramong channels seriously deteriorate performance of time-interleaved ADC. Consideringthe mismatch between the channels, many methods of detection and elimination of themismatch have been developed, but these methods have their own defects. In thisdissertation, an improved digital background calibration method with reference channelfor time-interleaved ADC is presented, based on least-mean-square (LMS) calibrationalgorithm. This method can calibrate sample-time error among channels as well as offsetmismatch and gain mismatch. This algorithm also has low computational complexity andthe ability to track out errors variations due to environmental changes and aging.Based on the needs of TIADC system, a14-bit100-MS/s single channel pipelinedADC using Chartered0.18-um single poly five layer metal CMOS technology isdesigned. With the single channel ADC and the digital background calibration algorithm,a14-bit400-MS/s time-interleaved ADC system is designed. Simulation of the TIADCsystem is done at the input frequency fin is equal to18.359375MHz and the samplefrequency fs is equal to400MHz, the results show that, signal to noise and distortion rate(SNDR) and spurious free dynamic range (SFDR) of the output signal of the TIADC aftercalibration improve46.24dBc and61.53dBc, reach85.22dBc and102.9dBc.