Research And Design Of Dual-loop Digital LDO Based On ADC+SAR

Modern system-on-a-chip(SoC)designs use multiple power domains to provide a regulated,regulated DC voltage to the subsystem.SoC require regulators with fast transient performance,low power,and integration.Low dropout regulators(LDO)have the advantages of full on-chip integration,smaller silicon area,and lower output voltage noise,making them one of the most widely used topologies.Compared to analog low dropout regulators(ALDO),digital low dropout regulators(DLDO)offer lower voltage operation,smaller area,easier process expansion,and the ability to achieve faster transient response.The control scheme makes it suitable for more sophisticated geometric digital intensive SoC.Traditional DLDOs have trade-offs between speed,accuracy,and power consumption,and are not immediately responsive to changes in output voltage.In addition,in order to improve the transient response,the output requires a large capacitance.In this thesis,the dual-loop controlled DLDO is used.The coarse-tuning loop is controlled by a variable reference voltage flash ADC.It can respond to output voltage changes immediately and provide large current conversion.The fine-tuning loop adopts a successive approximation register(SAR)structure,provides low output current,further improves adjustment accuracy and accurately achieves fast voltage regulation.The code controller eliminates the voltage ripple of the coarse tuning loop and prevents competition between the two loops.At the same time,in order to eliminate the limit cycle oscillation and reduce the quiescent current,the freeze mode is added after the fine adjustment operation,and the boundary detector solves the problem that the small load current step coarse adjustment loop adjustment fails.In order to improve the undershoot of the output voltage and the large undershoot caused by the binary search algorithm,an analog enhancement circuit is proposed.Since the analog enhancement suppresses the output voltage,the circuit can achieve no off-chip capacitance.The DLDO designed in this thesis is based on the SMIC 55 nm process for digital-analog hybrid design,and the layout design is implemented for the main circuit.And AMS is used for digital-analog hybrid simulation.The input voltage is 0.6V,the output voltage is 0.5V,the voltage difference is 100 mV,the load current range is 1mA-10 mA,the load regulation is 0.089V/A,the linear regulation is 0.059V/V,and the maximum quiescent current is 39.8uA.The maximum efficiency is 99.6%.When the load current jumps between 1mA and 10 mA at 3ns,the output voltage abruptly changes to a maximum of 97 mV,the response time is only 228 ns,and the circuit's figure-of-merit(FOM)is only 0.028 ps.Compared to the DLDO designed in other articles,the FOM of this article is reduced by an order of magnitude.At the same time,the circuit only has a capacitance of 1pF,the circuit area is small,and the overall performance of the circuit is good.