The Design And Implementation Of LDO With Fast Transient Response In 65nm CMOS Process

With the rapid development of the electronics industry,the scale of integrated circuits is increasing,and power management technology will become more and more important.The Low-Dropout Regulator(LDO)has the advantages of simple structure,small area,high PSRR,low power consumption and so on,which has become the main mode of nanotechnology VLSI power supply.Currently,the VLSI power distribution network(PDN)is during the distributed regulator stage,and the LDO becomes its core circuit.However,as the circuit scale becomes larger,PDN acts as the load of the LDO,which has a great influence on the stability of the output of LDO and affects the reliability of the entire power management network.Therefore,the focus and difficulty of LDO design is to improve system stability while ensuring fast load transient response.The LDO with fast response characteristics designed in this thesis is based on the background of the reliability of distributed LDO power distribution network research national ministry project.The basic structure and working principle of LDO circuit are analyzed.A LDO circuit with fast response characteristics is designed.It consists of reference voltage circuit,error amplifier circuit,buffer circuit,power adjustment tube and feedback circuit.The stability and transient characteristics of the LDO system have been improved.Based on the SMIC 65 nm CMOS process,the simulation result shows that the designed circuit meets the requirements of the index.An optimized impedance damping buffer is used in the LDO design to drive the power regulation tube.The dynamic-biased shunt feedback formed in the buffer reduces its output impedance,the drive capability of the power transistor gate is enhanced and the LDO transient characteristics are effectively improved.Using an insertion-optimized impedance damping buffer,the low-frequency pole is split into two high-frequency poles,which simplifies the system stability compensation method and enhances the stability of the LDO system.At the same time,the current buffer is used to compensate for the stability of the LDO so that the circuit remains stable over the entire load current range.The LDO designed in this thesis adopts a transient enhancement circuit to charge or discharge the gate of the power transistor,which can stabilize the output voltage quickly.A reference voltage circuit with a reference voltage of 0.8V is designed by using a current summing structure with circuit to suppress power noise,which has a good temperature coefficient and a high power supply rejection ratio.Folded cascode amplifier is used to compare and amplify the reference voltage and sampling feedback voltage.The high gain characteristics of this structure can increase the LDO power supply rejection ratio and load regulation rate.Finally,layout of LDO system is designed.This thesis adopts cadence tools to design LDO circuit and uses Spectre to simulate circuit module and system.The LDO circuit is designed and implemented based on SMIC 65 nm CMOS technology.The simulation results show that the input voltage of the design of the fast response LDO circuit is 1.4V~1.8V,the output voltage is stable at 1.2V,the maximum load current is 100 m A,the minimum pressure difference is less than 200 m V.T he load regulation is about 0.0099 m V/m A.When the load current is switched between 100?A and 100 m A,the output voltage overshoot and undershoot amplitude is within 5m V,and it can be stable to 0.34% within 5?s,which has a good transient characteristics and system stability.