Design And Implementation Of On-Chip Digital LDO With Fast Transient Response

In recent years,distributed low-dropout regulators?LDOs?have been extensively applied in SoC designs to provide power supply to the individual voltage domains of various IPs.In some ultra-low-power applications,analog LDO?ALDO?cannot obtain a suitable loop gain,but a digital LDO?DLDO?is more suitable for fine-grained power management in SoC due to its low-voltage operation capability and process scalability as well as a variety of control schemes to achieve specific circuit requirements.Such on-chip DLDO requires a fast load transient response because digital IPs that contain large number of fast-switching devices will impose drastic I_LOAD variations.However,the traditional DLDO faces the fundamental trade-offs among transient response speed,output current resolution and power consumption.When increasing the clock frequency for faster response,power consumption will increase proportionally,and current efficiency as well as loop stability will be reduced.And a large output capacitor for handling load transients is not conducive to on-chip integration.Therefore,it has become a hot research area for designers to design an on-chip DLDO with fast transient response.This thesis focuses on the fast transient response characteristics of DLDO,and two kinds of DLDO circuits are designed starting from synchronous control and asynchronous control schemes respectively.Firstly,a synchronous DLDO circuit based on tri-loop control is designed:three sub-sections of shift registers with carry-in/out operation are used as a digital controller for coarse and fine tuning to improve the trade-off relationship between speed and accuracy;and an auxiliary loop based on an undershoot detection and an AND gate is proposed to deal with load transients,resulting in faster transient response and lower undershoot voltage amplitude.In order to achieve faster adjustment speed and shorter recovery time,a DLDO circuit based on asynchronous and synchronous hybrid control is designed in this thesis an asynchronous flash shift register is employed in coarse tuning loop to improve adjustment speed;meanwhile,a“react-then-write”two-step dynamic logic is adopted for lower undershoot.To further shorten the loop delay,improve transient response speed and reduce undershoot voltage amplitude,a fast regulating method based on true single-phase clocked latch is proposed;a synchronous bidirectional shift register is adopted in the fine tuning loop to improve output accuracy;besides,a freeze mode is also employed to further reduce the power budget and to eliminate the limit cycle oscillation phenomenon,and a special counter is designed to reduce the steady-state output dc error.Two DLDOs designed in this thesis are based on SMIC 55nm process to complete the design and implementation of circuit and layout as well as simulation respectively.The simulation results show that:?1?The two DLDO circuits are able to work stably at an input voltage as low as 0.6V with a minimum dropout voltage of 50mV.Under the circumstance of a 0.6V-input and a 0.55V-output voltage,the line regulations of synchronous and hybrid DLDO are 20mV/V,21mV/V respectively,and the load regulations are 1.41mV/mA,0.216mV/mA respectively.?2?As for the synchronous DLDO,the undershoot amplitude is85mV with a 9.6-mA/10-ns load step and a total capacitor of only 20pF,thus the resulting figure-of-merit is 0.1337ps.The minimum quiescent current is 7.25uA and the maximum current efficiency is 99.92%.?3?As for the hybrid DLDO,the undershoot amplitude is 107mV with a 26-mA/2-ns load step,and it can recover within 20ns,the output dc error after stabilization is less than?1%.Compared with the references of the past two years,the synchronous DLDO designed in this thesis has certain advantages in figure-of-merit and current efficiency,and the hybrid DLDO has reached an advanced level in terms of transient response speed and recovery time.