Design Of Transient-enhanced Low-Dropout Regulator Based On SOI Process

With the rapid development of portable intelligent electronic devices,smart household appliances,smart grid and other fields,the demand for power management chips is increasing.As one of the important menbers of the power management chip,a low dropout linear regulator(LDO)is widely used in various electronic devices due to its low power consumption,low dropout,small area and low cost.The performance of the LDO directly affects the good and bad quality of the system.In this context,base on a domestic 0.13?m silicon-on-insulator(SOI)CMOS process,this paper studies and designs a high-performance LDO with enhanced-transient response of load.Firstly,the paper analyzes the stability and transient response of LDO.On this basis,based on tunable gate driving technology,a new circuit structure that enhances the transient response of the load is proposed in this paper,to improve the transient-response characteristics.Besides,to ensure the stability of the LDO,it adopts a buffer and the Equivalent Series Resistance generated by an off-chip capacitance to compensate its system frequency.As one of the important modules of the LDO,indexs such as temperature coefficient,power supply rejection ratio and accuracy of the reference voltage source directly affect the performance of the LDO chip.Therefore,this paper has conducted in-depth theoretical research on how to improve the PSRR of bandgap reference and how to reduce the impact of non-ideal factors on the accuracy of the output voltage.Finally,based on the above theoretical research,this paper presents an load enhanced-transient response LDO chip with a fixed output voltage of 2.8V and a maximum source current of 40mA.The schematic and layout of the LDO has been designed in a domestic 0.13?m silicon-on-insulator(SOI)CMOS process.The area without PADs is 0.009 mm2.Tools such as Calibre and Spectre are used to extract the parasitic parameters and verify the simulation.The simulations show that the LDO has features of a fixed output voltage of 2.8V,a response time less than 1?s with a maximum overshoot voltage less than 8mV when the load current rapidly changes from 0 to 40 mA,a phase margin of larger than 71°,a power supply rejection ratio(PSRR)of-53.5dB at low frequency,a load regulation of 50.15?V/mA and a linear regulation of 2.5mV/V.The bandgap of a less than 22.68ppm/? and a power supply rejection ratio less than-63.76dB.At present,the chip is in the testing phase.