The Research And Design Of On-Chip Digital LDO With Fast Transient Response

As a part of the power management unit in the system-on-chip(So C),the low-dropout regulator(LDO)plays an essential role in the performance of the entire system.Compared with analog LDO,digital LDO gets significant attention due to its low-voltage operation capability,insensitivity of PVT and process scalability.The traditional digital LDO using shift registers has a slow transient response,and increasing the sampling frequency leads to faster transient response but larger power consumption,which causes the fundamental trade-off between transient response and power consumption.The focus of this thesis is to improve the transient response of digital LDO,and the existing methods to improve the transient response of digital LDO is analyzed.A self-clocked binarysearching and linear-searching digital LDO and a digital LDO with asynchronous lookup and synchronous linear control are proposed.A coarse-fine-tuning technique is employed in the self-clocked binary-searching and linearsearching digital LDO.The coarse loop adopts a binary search algorithm and achieves fast transient response,and the fine loop obeys a linear search algorithm and obtains high accuracy.The self-clocked logic adopted in the DLDO eliminates the need for an external clock,which reduces the power consumption and removes limit cycle oscillation.To reduce the undershoot of the output voltage,an undershoot suppression circuit based on an AND gate is designed to reduce the undershoot of the output voltage by 52 m V.With the digital LDO demonstrated in a 40-nm SIMC CMOS process,the post-layout simulation results show that with the step load current alternating between 0.5 and 30.5m A with a 5-ns transition time,the proposed digital LDO shows a transient response time of 70 ns with an undershoot of 108 m V when the input and the reference voltages are 0.7 and 0.65 V.The quiescent current is 18.23?A,and the peak current efficiency is 99.94%.To further improve the transient response,a digital LDO with asynchronous lookup and synchronous linear control is proposed.The asynchronous loop based on event-driven can respond fast to the undershoot of voltage.The look-up table is the kernel module of the asynchronous loop,which its content is the PMOS array control word corresponding to different load current changes,and improves the transient response when output voltage undershoot occurs.The synchronous loop based on time-driven is used to fine-tune the output voltage and regulate the output voltage when undershoot occurs and overshoot occurs,respectively.A variable-gain accumulator instead of the traditional fixed-gain accumulator is employed in the synchronous loop,and reduces the recovery time of the output voltage overshoot by 35% and accelerate the transient response.To eliminate limit cycle oscillation,a limit cycle oscillation controller based on control word matching is designed,which improves the trade-off between steady-state ripple and accuracy.With the digital LDO designed in a 40-nm SIMC CMOS process,the simulation results show that with the step load current alternating between 1 and 31 m A with a 0.1-ns transition time,the proposed digital LDO shows a transient response time of 30 ns with an undershoot of 130 m V when the input and the reference voltages are 0.7 and 0.65 V.It achieves a peak current efficiency of 99.93% by consuming the quiescent current of 22.62?A.