Design Of A Capacitor-free Low Dropout Regulator

With the rapid development of electronic science and technology,power management technology plays a very important role in today's sciety.As a key technology of the integrated circuit,the high performance and low cost of power management chips are the important directions of the chip market.Low dropout regulator(LDO),is widely applied to various DC voltage stabilizing circuits for its low noise,high power supply rejection ratio,low power consumption,simple peripheral circuit and so on.Compared with the traditional LDO,capacitor-less LDO due to the structure of no external capacitance is easy to intergrate on SoC and has very lower cost,but because of the structure,transient characteristics and stability become a double challenge in circuit design.Firstly,the principle of LDO and the basic performance parameters were researched in this article;then the transient characteristics between the traditional LDO and capacitor-less LDO were mainly analyzed.Based on the research,a fast transient response capacitor-less LDO circuit was designed.The traditional LDO was composed of basic modules such as bandgap reference,error amplifier,Pass Transistor and so on.The structure of the transient enhancement circuit in the traditional LDO could be achieved without external capacitors and realized the function by adaptive load change.When the circuit was in normal operation,gate of the power transistor only needed a small current to work properly and would not occupy too much static current.when the load current changed suddenly,the transient enhancement circuit reflected the change of the load current to the control signal by using current mirror circuit so that the gate of output tube could achieve additional required current.As a result,the slew rate was increased so that the overshoot and subduction of the output voltage were suppressed.Therefore,this fast transient response,capacitor-less LDO improved the load transient response speed.In addition,an over-temperature protection circuit was added which improves the reliability of the circuit.Based on UMC 90 nm CMOS process,the circuit was built and simulated under the Cadence spectre platform.The simulation results showed that the input voltage of the designed LDO was 1.2V ~ 1.8V,the output voltage was 1V.When the load current changed suddenly,the overshoot voltage and the subduction voltage were less than 50 mV,and the response to steady-state time was less than 2?s.