Research On Key Technologies Of Single-channel High-speed Low-power SAR ADC

The next-generation mobile communication system(5G)challenges the design of analog-to-digital converters(ADCs),which requires the sampling rate beyond GHz,the effective number of bit(ENOB)of 6-8 bits and low power consumption for the endurance of mobile devices.Thanks to pipeline operation,pipelined ADCs have high throughput,which is the preferred structure of the GS/s sampling rate ADC.However,in order to maintain accuracy and linearity of the inter-stage amplification,high-gain and highbandwidth op amps are required,making low-power designs impossible.As the process scales down,the conversion speed of almost all digital successive approximation(SAR)ADCs has increased dramatically,while maintaining low power consumption.However,the conversion speed of a single-channel high-speed SAR ADC is limited by multiple comparison cycles.The time consumption of each comparison cycle is determined by the longer of the comparator's asynchronous logic cycle and the capacitive digital-to-analog converter(CDAC)settling time.In a comparison cycle,after the comparator completes the comparison,the comparator is reset,while the comparison result is passed to the DAC to start the corresponding switching.The next comparison must start after the comparator is fully reset and the DAC is fully settled.When the resolution exceeds 10 bits,the settling time of the MSBs DAC is usually the speed bottleneck.The subranging ADC quantizes the MSBs by a small DAC,and the comparison cycle does not have to wait for the MSBs large DAC to be settled well,thus the conversion speed is increased.The Detect-and-Skip(DAS)algorithm works perfectly with the subranging SAR ADC to significantly reduce switching and resetting power of DAC and improve linearity.This paper mainly studies the design of high-speed low-power subranging SAR ADC.The proposed DAS logic improves the speed of DAS and reduces overhead.By analyzing the distribution of codes in the subranging structure with gain mismatch,a simple calibration method is proposed to improve the robustness of the subranging structure.By consulting the literature,advanced techniques are implemented to improve the performance of the key modules of the SAR ADC,so that this work has achieved the state-of-the-art performance.Fabricated in a 40 nm process,the measurement results show that the 10-bit SAR ADC designed in this paper can operate at the sampling rate of 400 MS/s under a 1.2V supply.The power consumption of the ADC core is only 3.46 mW.At Nyquist,the ENOB of 9.08 and the spurious free dynamic range(SFDR)of 73.1 dB are achieved,leading to the Walden FoM of 16.0 fj/conv.-step.