Research And Design On High-speed Low-power SAR ADC

The high-speed analog-to-digital converter(ADC) is the key part of the data acquisition system, and it is also the main factor which affects the speed and accuracy of the data acquisition system. Nowadays the real-time signal processor requires the sampling rate of the high-speed ADC to be close to the intermediate frequency or radio frequency(RF), so that it can obtain as much information as possible. In many high-speed communication systems, like the Ultra Wideband(UWB), Orthogonal Frequency Division Multiplexing(OFDM), they all need the analog-to-digital converter to convert the RF signal to digital signal for the base band processing. In some communication protocals, like 802.15.4a WPAN(Wireless Personal Area Network), 802.15.6 WBAN(Wireless Body Area Network), more than Giga Hz bandwidth is required. To fulfill these requirements, in recent years many high-speed structures are proposed. Among them the successive approximation register(SAR) analog-to-digital converter(ADC) benefits a lot from the technology scaling thanks to its mainly digital characteristic. Combined with the time-interleave technology, SAR ADC can achieve more than Giga Hz sampling rate while still keeps a relatively low power consumption, becoming a very competitive counterpart in high-speed, medium to high resolution applications.This thesis mainly focuses on the design of high-speed low-power SAR ADC. Compared to other complex high-speed ADC architectures, this thesis proposed a compact high-speed low-power architecture. By segmenting the capacitor array into two parts, the high-weight codes are converted by small capacitors so that the DAC settling speed can be accelerated. Based on the segmented capacitor array architecture, a prequantization and bypass algorithm is applied to the segmented DAC array, so that the power and linearity performance can be further improved. The design is implemented in a 65 nm CMOS technology. The circuit level simulation results show that the ADC can achieve an ENOB of 9.52 bits and a FoM of 10.9fJ/Conv.-step with the sampling rate of 150MS/s and 1.2V supply.