Research On Key Technologies Of High-Speed And Low-Power SAR ADCs

Medium-resolution,low-power,small-area ADCs with several,tens,and even over a hundred of GHz sampling rate are required in many applications such as optical communication systems,high-speed serial links as well as vehicular millimeter wave radars to support their ultra-high throughput.For such goals,interleaved converter arrays with sub-channel SAR ADCs are exemplified as an optimal choice by the empirical data in recent years.Continuously increasing sampling rate and reducing overhead need faster single-channel SAR ADCs with higher or at least non-degraded power and area efficiency.With reduced number of channels,the calibration efforts and interleaving cost can be meaningfully reduced.The focus of this dissertation is on research on key technologies of high-speed and low-power SAR ADC.Two prototypes of SAR ADCs(10-bit 280MS/s and 8-bit 1.1GS/s)are fabricated in 40 nm CMOS processes.In Prototype-I,modified double-tail comparator,optimized digital-to-analog converter(DAC)capacitors arrary and transparent SAR logic are investigated for increasing sampling rate and decresing chip area and power.The measured results show the peak SNDR and SFDR is 54.55dB and 67.52dB,and peak ENOB is 8.77 at 1.2V supply when sampling clock is 280MS/s.In Prototype-II,a latch-based SAR logic and an offset calibration technology which acts on DAC are proposed for a high-speed two-step SAR ADC with passive residue transfer technique.The demonstrated ADC achieves high sampling rate with high efficiency in terms of both power and area.Prototyped in a 40-nm CMOS process,this ADC occupies only 22x75μm~2.With a 580 MHz input sampled at 1.1 GS/s,it exhibits a SNDR of 45 dB and a SFDR of 66 dB under 4.0 mW power consumption,leading to a FOM_W of 25 fJ/conv.-step.The measured effective resolution bandwidth is larger than 3 GHz.