Digital Background Calibration Algorithm For Pipelined Analog-to-Digital Converters

In various structures of analog-to-digital converters (ADCs), pipelined ADC has been used in many applications due to its high resolution and speed. These applications include video images processing system, wireless communication system, digital transceiver station and so on.Pipelined ADC, however, is affected by a variety of non-idealities. And with the process size and supply voltage reducing, these non-idealities have posed a serious challenge to the design of analog circuits. Therefore, people began to use a variety of assistive technology to correction or compensate the analog circuit errors. In a variety of digital assisted correction techniques, digital background correction is currently the hot research area. It can monitor and correct the errors introduced by the changes of the environment without interrupting the normal work of the analog circuit.In this thesis, the non-idealities of the ADC are analyzed, and then it proposes a correlation-based digital background calibration algorithm using pseudorandom noises injections. The calibration is aimed at correcting the errors introduced by capacitors mismatches and residue amplifier distortions. The pseudorandom noises are injected to the multiplying digital-to-analog converter (MDAC) and suffered from the non-idealities in the MDAC, and then reflect in the digital output. The errors can be picked up in the backend digital process and compensated the final output of the ADC through the correlation-based method. Compared with the conventional methods, the proposed calibration method can pick up the errors information of the capacitor mismatches and residue amplifier distortions integrally with only one group of pseudorandom noises injections. Meanwhile, special pseudorandom sequences are used to meet the effect of the calibration algorithm and made to have a fast convergence time. The1st stage of the pipelined ADC is improved to solve the contradiction between the magnitude of the pseudorandom noises injections and the input signal range. Simulation results of an ADC model show that, after calibration, SFDR is improved from55.5dB to98.5dB, and SNDR is improved from41.8dB to78.2dB.Finally, the circuit-level of the pipelined ADC is analyzed and designed. A sample/hold circuit with high linearity MOS switch is proposed, a high gain bootstrapped amplifier and other blocks of the ADC are designed. Simulation results of the circuit-level ADC show that it achieves12.685bits ENOB and87.026dB SFDR.