Design Of 7.5～15GHz Fractional Frequency Divider For Wideband Phase Locked Loop

In the field of wireless communication,phase-locked loop frequency synthesizer module provides stable and accurate local oscillation signal in RF transceiver system,and its performance directly affects the working status of the whole system,which gradually becomes a hot spot for research in the industry.With the rapid development of communication technology,different fields such as mobile communications,radar systems and satellites are divided into their own communication protocol standards,the development of a broadband phase-locked loop that can cover a variety of communication protocol standards has become a trend,the phase-locked loop frequency range,resolution,phase noise and fractional spurious and other indicators are also increasingly high requirements.As one of the important modules in the phase-locked loop,the fractional divider determines the performance and application scenarios of the phase-locked loop.In this paper,we study the fractional divider in wideband phase-locked loop.This paper designs a high performance fractional frequency divider.The high speed divider part features high operating frequency,wide operating frequency range,large range of continuous frequency division ratio and low phase noise,which can realize high precision fractional frequency division ratio with programmable sigma-delta modulator.The high-speed divider includes a 4/5 dual-mode divider,a 17-bit pulse counter and a 2-bit swallow counter.4/5 dual-mode divider is designed with current-mode logic structure and combines primary and secondary latch size asymmetry technology and embedded logic gate technology to increase the maximum operating frequency.The pulse counter has a large number of bits,and the design proposes a current-mode logic structure based on the current-mode logic structure with a bit-setting end/2 divider and a multi-input and gate detection logic circuit to improve the operating speed and ensure the correct counting function.In addition,a multi-stage noise shaping structure is used to design a sigma-delta modulator with adjustable order 1 to 4,where the bit width of each accumulator is programmable in the range of [1 to 32] for flexible selection for adjustment,and a compromise between power consumption and quantization noise can be made according to the application requirements,while a random number generator circuit is added to suppress fractional spurious.The fractional divider proposed in this paper is based on 0.13 um Si Ge Bi CMOS process,and the circuit design,layout design,before-and-after simulation and flow test are completed.The post-simulation results show that with the supply voltage of 3.3V,the fractional divider of this design can be correctly divided at 16～524287 continuous dividing ratios at 6GHz～18GHz under voltage and temperature pull bias.The fractional divider is applied in 7.5GHz～15GHz wideband phase-locked loop,and the test results after flowing the chip are that the phase noise of the phase-locked loop output can reach-115.34 d Bc/Hz@1MHz under 15 GHz,and the phase noise of the high-speed divider is about-158.8d Bc/Hz@1MHz,and the fractional spurious can be suppressed below-80 d Bc when the fourth-order modulator and random number generator are turned on.can be suppressed below-80 d Bc.The post-simulation and test results all meet the design specifications.