Design Of 50Gb/s PAM4 Serdes Receiver

Massive data put forward higher requirements for transmission bandwidth of data centers.In the next generation of 400G Ethernet,the transmission data rate of a single lane must reach more than 50G/bs,serial transmission systems based on NRZ signals can no longer meet the bandwidth requirements.While fourth-order pulse amplitude modulation technology(PAM4)is widely used in ultra-high-speed serial tranceiver systems above 50Gb/s because of its bandwidth compression characteristics.This thesis studys50Gb/s PAM4 signal serial communication receiver design using 65nm CMOS technology.PAM4 receiver in this thesis includes combination equalizer consists of continuous-time linear equalizer(CTLE)and 1-tap decision feedback equalizer(DFE).CTLE adopts a source-level capacitor degradation structure to expand bandwidth.In the design of DFE,a voltage shifting and limiting amplifiers are specially designed for the four voltage levels of PAM4 signal,which can determine four voltage levels and generate three thermometer codes,and then use CML latches and adders realizing 1-tap DFE feedback compensation.PAM4 receiver in this thesis also includes clock recovery circuit(CDR)and decoder design.CDR adopts PLL loop structure work at 25Gb/s data rate.CDR mainly includes Bang-Bang phase detector(PD),voltage-current converter(V/I),low-pass filter(LPF)and voltage-controlled oscillator(VCO).The high-speed XOR gate in the PD adopts a completely symmetrical structure to avoid static phase maladjustment,and the voltage-controlled oscillator adopts LC structure to gurantee good phase noise characteristics.The decoder circuit adopts a three-input exclusive OR gate with a special flattened structure,which has the advantage of large bandwidth and can working correctly at 25Gb/s,.This thesis also completes the layout design and post-simulation of the entire receiver.The layout area(including the pad)is 375mm~2,and the power consumption is 320m W at 1.2V.The combined equalizer circuit can equalize the PAM4 signal to an eye diagram horizontal opening of 0.45UI.In the clock recovery circuit,the phase noise of the VCO at 1MHz is 104.9d Bc/Hz,the recovered clock jitter is3.2ps(0.08UI)<0.1UI,the recovered data jitter is 3.6ps(0.09UI)<0.1UI,and the decoder outputs two lane NRZ signals with an eye opening of 0.8UI.