High-speed Low-power Embedded Sram Design

Embedded memory is an important part in SoC, and the ratio (Area) of embedded memory which takes part in SoC increase with manufacture process scaling down. About 90 percent area of SoC will be located with variety memory in 2010 year. SRAMs become a critical part in SoC because of its high density, high speed, low power and its manufacture compatible with logic process. Recently, for meeting hand-take equipment and high performance processor requirement, SRAMs as an important part, the speed and power consumption are very important parameters in specification of products. High-speed and low power techniques become dominant in SRAMs design.This paper makes a summary about SRAMs high-speed and low power design technique and its relative products. There are also detail describe and analysis about basis operation principle of SRAM, SNM of SRAM cell, the layout partition of SRAM array and the design of SRAM perpherial circuit. Based on analysis of two type circuit of address decoder, a new high-speed, save area pre-decoder has been employed. In order to decrease offset voltage effect in sense amplifier because of mosfet mismatch in deep micro process, a voltage-latch type sense amplifier which has pre-amplify has been employed, and improve the stability of system operation. By analysis of several architectures of advanced SRAMs, the tracking scheme principle of SRAM and its application have been detail presented; And raise a more excellent tracking scheme to implement high-speed, low power design of SRAMs. The papers also present the sources of power consumption and two methods of decrease power consumption, and make an evalution of SRAM power dissipation. The whole chip layout floor plan, signal plan and power plan are also disussed in this paper at the view point of design; It make sure the quality of layout. For high density verification of SRAMs, there are two methods to effectively improve simulation accuracy and speed.The SRAM, having a chip size of 1.44mm X 1.07 mm and having density of 16384 words, 32 bit, column mux 32, is fabricated by using 0.13um twin-well single-poly and eight-metal CMOS technology. The chip which implements layout access time is 4.69ns by HSPICE simulation. The whole chip operation current is 50 mA when the frequency is 150MHz, and has advantage of small area compare to similar products.