Custom ASIC Design of Static Random Access Memory (SRAM)

SRAM is highly used as today's CPU memory's cache, so to design a highly efficient and low-cost SRAM is every company's dream in order to increase the computer's computing ability to meet every area's satisfaction. This paper is mainly about how to design a custom ASIC SRAM and test this design by computer simulation and to analyze the advantage by comparison to 16 FO4 and power consumption. This paper first of all introduces what SRAM is and why it is so important to utilize it. And then a explanation of my design of SRAM will be given step by step including the whole floor plan, actual design of SRAM which includes flip-flop, decoder, bit-line reset, bit-line muxs, sense amplifier, write driver, output mux, sense amplifier enable generation, block selec generation, write-through control generation, bit line reset control and decoder evaluate control generation, local block-selec and write enable generation, ecc, inter-connection, etc. And at last, we will have a test for this design as well as the performance and results.