Design And Implementation Of A High Performance Clock And Date Recovery Circuit

The application of real-time communication and stream media give a strict requirement on the rate and the quality of the data,which stimulate people to design higher performance I/O circuits.The clock and data recovery circuit is the critical part of high quality serial interface circuit,the design of which is full of challenge.This thesis presents the design and implementation of a 2.5Gbps full-rate PLL-based clock and data recovery circuit.The system specification can be decomposed into several parameters by system modeling.The optimal loop parameter damp ratio(ζ) and loop bandwidth(ω_n) is derived by analyzing the phase noise properties of individual components and the loop transfer characteristics,which make the output jitter of the system the least.In this CDR structure,the full-rate phase and frequency detector make the requirement of system clock duty cycle not too strict.The symmetric load voltage control oscillator (VCO) Which operate under the self-bias circuit have a good rejection function to the power noise,Witch makes less total jitter of the system.The high speed output buffer solves the problem of the low swing output of VCO.The whole system of CDR was implemented in 0.13um digital CMOS process.It operates with the bit rate of 2.5Gbps,and the simulated RMS and peak-to-peak jitter of the CDR are 0.822 ps and 3.140 ps,respectively,with 2³¹-1 Pseudorandom NRZ data bits.The power consumption of the whole system is 58mW,and its area is 176×240μm².the simulation results meet the requirement of the design SPEC.