FPGA Implementation And Performance Research On QC-LDPC Codes Based On QR Codes

Quasi-cyclic low-density parity check(QC-LDPC)codes are an important class of structured LDPC codes,which can save a lot of storage resources when implemented in hardware.However,there are still some problems in the traditional QC-LDPC codes,i.e.the waterfall region has better performance but the error floor region is worse or the performance of error floor region is very well but the waterfall region is worse.In recent years,researchers have used the parity check matrix of Reed-Solomon(RS)codes as the base matrix to construct QC-LDPC codes with longer code lengths that have better performance in both the error floor region and waterfall region.Quadratic residue(QR)codes and RS codes are subclasses of BCH(Bose,Ray,Hocquenghem,BCH)codes,with rate slightly greater than 0.5,perfect algebraic structure,large minimum Hamming distance and strong error correction capability.Therefore,it is expected that the excellent QC-LDPC codes of high rate can be constructed based on the QR codes.In this thesis,the corresponding encoder and decoder are designed for the QC-LDPC codes based on QR codes.The main work and innovation are as follows:1.By analyzing the short cycle distribution of Tanner graph of QC-LDPC codes based on QR codes,a QC-LDPC code with excellent performance can be found,and then the FPGA implementation of its encoder and decoder is researched.2.The encoder is designed based on the circuit of Shift Register Adder Accumulator(SRAA).Then,the thesis improved SRAA circuit and designed an improved serial encoder.3.Compared with other QC-LDPC codes at the same rate,QC-LDPC codes constructed based on QR codes have larger row weights,which means that more resources will be consumed in hardware implementation.In order to solve this problem,the decoder is implemented by layered normalized min-sun algorithm(LNMSA)which consumes lower resources relatively.The quantization scheme of the decoder and the correction factor of LNMSA are determined through experiments.4.The decoder uses a partial-parallel structure to simultaneously process consecutive p rows of a layer.On the storage structure of variable node posterior probability information,the continuous p information is combined into one group and the consecutive two groups are alternately stored by two RAMs.When the minimum value and the sub-minimum value are obtained,the input message is split into 4 groups,and then the global minimum value and the sub-minimum value are compared by respectively obtaining the minimum value from the 4 groups,thus effectively reducing the complexity of the comparison operation of the minimum value and the sub-minimum value.