Design Of LDPC Code Coder And Decoder Based On Partial Reconfiguration FPGA

With the development of 5G communication technology,the communication rate is getting higher and higher.The frequency of the signal is also getting higher and higher,and the channel environment and signal attenuation are getting worse.In order to meet higher requirements for communication reliability,a more efficient channel coding method is needed.At the same time,with the continuous development of FPGAs,more flexible and efficient FPGAs are more widely used in 5G.Based on the LDPC code of eMBB scene in 5G,this paper studies the codec design of LDPC code based on reconfigurable FPGA,and explores the hardware solution to improve communication reliability.This paper first introduces the current research status,future development changes and research significance of LDPC codes and partial reconfiguration.Then the relationship between the base map and the spreading factor is analyzed for the LDPC code in the eMBB scenario in 5G,and the direct encoding algorithm of the LDPC code is given according to the characteristics of the base map.For the decoding algorithm of LDPC code,this paper mainly compares the performance difference between SPA algorithm and MSA algorithm.This paper adopts MSA algorithm which is easy to implement by FPGA.Secondly,this paper studies the basic theory of partial reconfiguration,including the design constraints of partial reconfiguration,the design flow and the parameters and principles of the controller IP core.Then,the relevant parameters of the LDPC code codec are first determined,and then the input signal and the output signal of the LDPC code codec are specified according to the design constraints of the partial reconfiguration.On this basis,the reconfigurable design of the check digit generation module in the LDPC code encoder and the reconfigurable design of the check node update module and the variable node update module in the decoder are completed.Then,based on the reconfigurable FPGA,partial reconfiguration in multiple control modes is implemented,which are partial reconfiguration in JTAG mode,partial reconfiguration of PL-side control bitstream loading,and partial reconfiguration of PS-side control bitstream loading.In addition,the advantages and disadvantages of the above three partial reconfiguration implementation methods are analyzed.The partial reconfiguration method of the PS end control bit stream loading is used to implement LDPC code encoders and decoders with different code lengths.Finally,an LDPC code encoder that can transform the code length is designed.This paper mainly uses the code lengths of 104 and 208,and uses the direct coding algorithm.Then the MSA decoding algorithm is used to design the LDPC code decoder which can transform the code length.The input information processing module,the verification node update module,the variable node update module and the control module are designed and implemented.Then,the LDPC code encoder which can transform the code length is actually tested on the ZC706 development board,and the dynamic switching of different coding modules can be realized through verification.