Research And FPGA Implementation Of The LDPC Encoder And Decoder Based On IEEE802.11n Protocol

To improve the reliability of signal transmission,channel coding technology becomes one of the effective ways and the LDPC has been the best code pattern because of its excellent performance in the middle and long codes,which has been used in wireless communication,satellite communication and so on.Currently,it is of very important theoretical value and practival value to research and design the LDPC that has good decoding performance and low complexity in hardware implementation.First of all,according to the twelve kinds of check matrixs in IEEE802.11n protocol,this paper designed and implemented the encoder in SMIC 130-nm CMOS technology with an area of 0.67mm~2 based on the RU coding algorithm by using the1.56 KB RAM to save the check matrix after researching and understanding the coding algorithms,and the encoder was verified by FPGA.Next,this paper also researched the initialization algorithm of LDPC decoder,derived and summarized the soft demodulation formula of BPSK,16-QAM,64-QAM.At the same time,researched the quantification for LDPC decoder initial information and determined the design by Matlab simulation.Last,this paper came up with the linearizated decoding algorithm called linearizated Log_BP algorithm which is shown good performance when the code length is short,code rate is low and iteration number is small among the LDPC decoding algorithms,such as BP,Log_BP,Min_Sum algorithms.Finally,according to the twelve kinds of check matrixs in IEEE802.11n protocol,this paper designed and implemented the decoder in SMIC 130-nm CMOS technology with an area of2.14mm~2 based on the Min_Sum algorithm by using the 1.5KB and 3KB RAM to save the check matrix and channel information respectivly,whose max-throughput is0.667Gbps and was verified by FPGA.