Design And Implementation Of Multi-rate SC-LDPC Code Encoder And Decoder

Channel coding is an important means to improve the reliability and effectiveness of communication.Finding a channel coding with good performance has always been the focus of communication system research.Spatially Coupled Low-Density Parity-Check(SC-LDPC)codes are a new type of channel coding based on LDPC codes.Compared with LDPC codes,they have better performance gains and broad application prospects.However,the current research on SC-LDPC codes mainly focuses on the theoretical aspects,and there are few related researches on practical applications.In view of the above problems,this paper studies the multi-rate hardware implementation of SC-LDPC codes,which is mainly divided into three parts:check matrix construction,encoder algorithm design and hardware implementation,decoder algorithm design and hardware implementation.Construct a SC-LDPC code with good performance and complete the design and implementation of encoder and decoder based on FPGA.The main content of the paper is as follows:First,analyze the multi-rate compatibility scheme of SC-LDPC codes,refer to the structure of the check matrix of 5G NR LDPC codes,and construct a SC-LDPC code coupling base matrix compatible with three code rates.By selecting the non-zero elements of the coupling base matrix,a coupling sub-matrix is generated,and finally a complete SC-LDPC code check matrix is formed by coupling.The check matrix has a Raptor-like form,can use the check matrix for system coding,and has a performance improvement of about 0.2dB compared with the 5G NR LDPC code check matrix corresponding to the same code rate,and has good decoding performance.Then,on the basis of the multi-rate SC-LDPC code check matrix constructed in this paper,combined with the traditional SC-LDPC code encoding algorithm,design an encoding algorithm suitable for multi-rate SC-LDPC codes,and design the various modules of encoder according to the algorithm.Simulate and synthesize the encoder on the Vivado platform to verify the functional correctness of the encoder function.Then,use different SC-LDPC decoding algorithms to perform performance simulation analysis on the multi-rate SC-LDPC code check matrix constructed in this paper,and select a decoding algorithm suitable for hardware implementation to complete the decoder design.Simulate and synthesize the decoder on the Vivado platform to verify the correctness of the decoder function.Finally,the encoder and decoder of the multi-rate SC-LDPC code are tested independently based on FPGA,and joint testing is performed on the basis of meeting the design function.Under three different code rates,the normalized signal-to-noise ratio is at 4dB,the bit error rate of the decoder is less than 10^-4 orders of magnitude,which meets the system design index.