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The Design Of QC-LDPC Encoder And Decoder On FPGA And Its Application In Cooperative Communication System

Posted on:2014-09-01Degree:MasterType:Thesis
Country:ChinaCandidate:H ChengFull Text:PDF
GTID:2298330422980612Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
Doctor Gallager described LDPC codes in his PhD theis in1963. This kind of codes have aperfect performance that close to the Shannon limit, but because of the restriction of the hardwaretechnology, LDPC did not get enough attention. Since Mackay, Spielman and Wibergre-discovered the LDPC codes in1996, it receives widespread attention both in academia andindustry applications, setting off a wave of channel coding research community. With the currentdevelopment of hardware technology, LDPC codes have been widely used in the fourth generationmobile communication systems, satellite communications, network coding cooperativecommunication systems, CMMB and other communication systems.The research on LDPC codes of the hardware implementation has made a tremendousdevelopment, but whether the iterative coding algorithm encoder or the serial structure and fullyparallel structure decoder has its own drawbacks. QC-LDPC code as a subclass of the LDPC codehas its own characteristics. Taking full uses of quasi-cyclic characteristics of QC-LDPC codes,scholars and experts have developed a encoder based SRAA structure and a TPMP layereddecoding algorithm and its related decoder structure, greatly reduces the hardware resourcesconsumption and maintain the performance advantages at the same time.Firstly, we introduce the linear block code, then derived the basic theory of LDPC codes, andfocus on constructing QC-LDPC codes based on finite fields.Secondly, we introduce various kinds of encoding methods and decoding Algorithms ofLDPC codes, then simulate and compare the performance of the different kinds of decodingAlgorithms. We also determine two correction factors about two optimize Algorithms based on theminimum algorithm. We finally choose layered decoding algorithm based on normalized MSA todo the hardware implementation, processing using the7bits quantified data.Thirdly, we presents the QC-LDPC code based on the additive group of finite field andthrough a special method,we construct a full rank QC-LDPC code and used it in codingcooperative communication systems at the source node and the relay node, thus constructs ageneral check matrix. Then we derive the double Tanner graph andwe adopts the joint iterativedecoding algorithm based on the double Tanner graph the destination node. We also simulate andcompare the performance of various ideal and non-ideal cooperation communication systems.Finally, basing on Quartus II software, we use verilog HDL language and achieve the QC-LDPC codes codec layout and integrated optimization on Altera’s EP3SE260F1517C2device.We also use Modelsim do simulation tests. At the operating frequency of70MHz, the throughputof encoder can reach139.45Mbps. While the iteration of the decoder is5, the operatingfrequency is set at35MHz, the throughput can be achieved104.175Mbps.
Keywords/Search Tags:Finite field, QC-LDPC code, SRAA structure, hierarchical decoder, FPGA
PDF Full Text Request
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