Research And FPGA Implementation Of LDPC Encoder And Decoder In High Speed Statellite Communication

LDPC codes have attracted wide attention due to its high bit rate,high coding gain and low error floor,in near earth satellite communication systems.One major problem hinder the application of LDPC in satellite communication systems is how to improve the throughput of LDPC with limited hardware resource.This paper designs and implements a LDPC coding and decoding system in FPGA.The encoding and decoding system can work in the error floor area under AWGN channel,when Eb/N0=5dB,and the throughput is greater than 300 Mbps.In this paper,we first study the LDPC encoding and decoding algorithm,and compare them in two aspects: bit error rate performance and computational complexity.According to the design requirements of the system: high throughput and large signal to noise ratio,the structure of coding and decoding method is selected to complete hardware implementation of the CCSDS standard(8176,7154)LDPC code.Then,according to the actual engineering conditions,a MSA model with memory reading and writing error is proposed,because of the memory reading and writing errors in FPGA.The symmetry condition of the model is verified,and then the density evolution algorithm is used to analyze the model.The analysis results show that the memory reading and writing error will reduce the noise power threshold of the MSA algorithm,decrease the convergence rate and increasing the level of error floor which will be no lower than the memory error rate.And the decoder parameters are determined according to the new model.It is proved that the decoder can work normally when there are error in memory reading and writing process,and the performance meets the design requirements.Finally,a high throughput LDPC encoder and decoder is designed.An encoder supporting continuous data input is designed by using SRAA.The decoder of 7×16 column parallelism and 7×2 row parallelism is designed and implemented.The parallel serial circuit separation method in the decoder design process greatly improves the decoder throughput.At the same time,a method of solving memory conflicts by cyclic storage is proposed,which saves hardware cost.Finally,the encoder output is sent to the decoder through the AWGN simulation module.The error code was not found under the Eb/N0=5dB condition.