Research On Key Techniques Of Millimeter-Wave PLL Frequency Synthesizer

Broadband satellite communication systems are widely used in television broadcasting,global positioning navigation,broadband communications services and remote sensing mapping services.In order to improve the system bandwidth and communication data rate,the industry is currently exploring the application of Ka band to broadband satellite communication systems.This application places more stringent performance,power,and area requirements on millimeter-wave wireless transceivers.In a millimeter wave transceiver,a frequency synthesizer providing a local oscillator signal is one of the most important modules,and the quality of the output local oscillator signal has a great influence on the performance of the transceiver system.This article will focus on the key technologies applied to the 22 GHz wireless receiver system and 30 GHz wireless transmitter system PLL frequency synthesizer.In this thesis,the frequency domain or z domain models of the main modules in the analog phase locked loop are introduced in detail,and the input and output signal gain and the transfer function of each noise source to the output of the phase locked loop are deduced.Thus,a more comprehensive and in-depth understanding of the noise performance of the loop can be obtained,and based on this,the frequency-division ratio allocation of the frequency-dividing link,the amplitude-frequency and phase-frequency response characteristics of the loop filter,the characteristics of the loop filter,can be improved.Meanwhile,phase frequency detector and charge pump matching degree,oscillator noise level and other performance indicators will be better.This thesis analyzes in detail the working principle,existing problems and current research progresses of oscillators and charge pump core modules in millimeter wave analog phase-locked loops.Then the corresponding optimization techniques are proposed for the respective problems.Simulation results show that the proposed optimization technique for the 22 GHz negative transconductance oscillator reduces the phase noise at 1MHz offset to-100dBc/Hz in the frequency tuning range of over 2GHz.The optimization technique proposed for the 10 GHz Class C oscillator reduces the oscillator power consumption to 4.5mW while reducing the phase noise to-112dBc/Hz or less and the FoM value to-190dBc/Hz.In addition,the optimization techniques proposed in this thesis for differential charge pumps and high-supply voltage charge pumps have reduced their transient mismatch to around 5‰.In this thesis,the optimization techniques proposed for Oscillator and Charge Pump are applied to 22 GHz phase-locked loops and 10 GHz phase-locked loops,respectively.The 22 GHz phase-locked loop is TSMC 90 nm process tape verified.The test results show that the phase-locked loop covers the frequency range of 20.3-22.5GHz and can complete fast locking.In the required frequency range,the phase noise at the 1 MHz offset of the output signal of the PLL is about-97dBc/Hz.The 10 GHz phase-locked loop is completed using the TSMC 65 nm process.Loop transient simulations on the cadence simulation platform show that the PLL can lock at about 30?s at different fractional frequency division ratios.Because of the extremely low power consumption of Class C oscillators,the overall DC power consumption of the phase-locked loop is only 14.4mW.