| With the wide application of the WIFI standard,the low power demand of WIFI chips cannot be ignored.Therefore,the low cost and low power consumption WIFI chip has a considerable market prospect.The clock generation circuit serves as a part of the RF front-end of the WIFI chip.The clock generation circuit is usually realized by a frequency synthesizer,which providing a reliable clock signal for the mixer.In this thesis,the basic conception of frequency synthesizer is introduced first,and then the basic situation of the oscillator is given.Currently,LC VCOs are widely used in RF circuits,so this thesis introduces the important passive devices in LC VCO.Then the noise of the oscillator is analyzed and the method of calculating and simulating the noise of the oscillator summarized by the author is given.Finally,a wideband high-performance transformer based VCO is given,and a simplified wideband oscillator is designed.The chip photo is shown,and the test results are briefly introduced in this thesis.In this thesis,the design specifications of low power frequency synthesizer for WIFI are analyzed.The structure of frequency synthesizer and some important parameters are determined according to the specification.The method of using automatic amplitude control to reduce power consumption is introduced in this thesis.Then the specifications of each module are defined from top to bottom,and the circuit design and layout design of some important modules are completed according to the specification,the simulation results and the layout of some important modules are given.Finally,using the TSMC 40 nm 1P6M process,the power consumption of the frequency synthesizer designed in this thesis is 2.3mA in general,and 2.84 mA in the worst case.Compared with the circuit that does not use automatic amplitude calibration,the power consumption has a reduce by about 20%.In general,the integral phase noise is 0.68° and the worst case is 0.87°.Other performances satisfy the requirements of the 2.4G WIFI LO. |
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