The Key Technology Research For Low Power Frequency Synthesizer

With the development of wireless communication technology, the demands for wireless handheld device increase continually, which lead to appearance of various short range wireless standards, such as wireless local area networks, Bluetooth and Zigbee. The chips with lower power and lower costs become the key competitive fact in wireless system. Frequency synthesizers supply local oscillation signals for radio frequency transceiver, and realize frequency modulation, which influence performance of the whole wireless system significantly. Usually, high performance frequency synthesizers are implemented by charge-pump phase locked loop (PLL) or all-digital phase locked loop (ADPLL), thus we focus on these two frequency synthesizers and their building blocks, studying the key technologies for low power, low phase noise and low costs by theory analysis and measurements.Voltage controlled oscillator (VCO) is the core circuit of frequency synthesizer, which phase noise is the most concerned. Prior designs reduce phase noise at the cost of larger power and area, whereas this paper aims to achieve low phase noise with low power. In advanced CMOS process, the influence of flicker noise is more significant as the transistor size scaling down, thus people pay more attention to reduce flicker noise from tail current source or cross-coupled pair. An improved self-switched biasing VCO is proposed, which not only reduce flicker noise from tail transistor, but also suppress the up-conversion from cross-coupled pair. Since the flicker noise from the two main sources are reduced simultaneously, the phase noise at10kHz offset achieves-77.6dBc/Hz. Tade-off between phase noise and power consumption in conventional switched-biasing VCO leads to huge power for low phase noise, the proposed breaks the limitation and gets low power. The circuit is implemented in0.18μm CMOS technology for2.4GHz Zigbee application, which measurement results show the positive effects for low phase noise and low power by proposed techniques.A low power and low complexity two point modulator is designed for frequency modulation in Zigbee transmitter, which is based charge-pump PLL. Calibration circuits are required in traditional two point modulator to reduce gain mismatch, which increase power and complexity. A modulation structure is proposed, which gets low gain mismatch by reducing the mismatch of varactors and improving the linearity of frequency modulation gain. Compared to other solutions, the proposed technique does not require additional calibration circuits, thus complexity and power is reduced. Another key building block of two point modulator is Delta-Sigma modulator, which noise shaping and spur performance are verified by different orders, topologies and input bits. Phase-frequency detector (PFD) and charge-pump with high linearity is adopted to suppress the noise folding in fractional-N frequency synthesizer. The two point modulator is fabricated in0.18μm CMOS technology, and the measurement results are compared with other works.ADPLL exhibits many advantages than charge-pump PLL in advanced CMOS process, such as low costs, easier to intergrated for system on chip and so on. Usually, ADPLL with wide range frequency output uses Bang-Band PFD for low power, which can only realize integer division with worse phase noise, existing stability problem. A TDC with adjustable resolution and power consumption is proposed for the first time, which is used in our low power and wide-band ADPLL for fractional-N division, while this is invalid in conventional wide-band ADPLL with Bang-Band PFD. Additionally, phase noise and stability is improved in proposed ADPLL. The ADPLL is implemented in40nm CMOS process, which is verified by simulation results.