Time-interleaved Adc Design And Calibration Studies

High-speed analog-to-digital converter (ADC) has wide applications in high-speed data communication, LCD driver, digital oscilloscope, hard disc driver, etc. With the increase of speed of these instrumentations and devices, the parameters, such as higher speed, lower power, better performance, are required on the ADCs used in them. Otherwise, the bandwidth is limited to certain kind of process level, so the corresponding speed of ADC is also finite. For improving the speed of ADC, time-interleaved architecture can be applied on the design of ADC.This dissertation gives a series of research results on the design and correction of time-interleaved ADC. Firstly, the non-ideal effects, such as offset mismatch, gain mismatch, sampling-time mismatch, have been analyzed.Subsequently this dissertation gives a design example-a 1-GS/s, 6-bit time-interleaved ADC, which can be used in ultra wide band (UWB) wireless communication. Two channels constituted this ADC, and single channel was realized with folding and interpolation architecture using cascaded folding blocks and active interpolation techniques. A front-rank track-and-hold (T/H) circuit is used to avoid the sampling-time mismatch between two channels. Sharing reference and bias circuit is applied to reduce offset mismatch and gain mismatch between two channels. Improved bootstrapped switch is used to increase the dynamic performance of sampling, and suppress the clock-feedthrough effect.This chip was fabricated with SMIC's 0.13-μm, one-poly 8-metal (1P8M) mixed-signal CMOS process. By verification testing, the chip has right conversion function under 1-GS/s. The measured effective number of bits (ENOB) and spurious free dynamic range (SFDR) achieves 5.18bit and 41.57dB at 10MHz input and 4.81bit and 36.91dB at 500MHz input (Nyquist input frequency) respectively. The ADC core consumes a power of 66-mW under 1.4-volt supply and occupies 0.45mm area.This dissertation has also summarized variable calibration methods and given some research results on the digital background calibration of time-interleaved ADC. A digital background calibration method for minimizing timing and gain mismatches effects in two-channel time-interleaved ADC is presented. Matlab simulations demonstrate the effectiveness of the proposed method.