Design Of 18Bit 3M S/S High-Precision Analog-to-Digital Converter

As the performance of digital circuits improving,digital processing has become the mainstream.However,most of the original signals are analog signals,so the demand for high-performance analog-to-digital converters is growing.Pipelined SAR ADCs are drawing more and more attention in the design of high-performance ADC due to its combination of Pipelined ADCs'high speed and precision and SAR ADCs'small area and power consumption.In this paper,an 18-bit 3M S/s high-precision analog-to-digital converter with two-stage Pipelined SAR structure is designed,and it uses a V_cm-based sampling scheme to greatly reduce the energy loss of the quantization process.In the design of first-stage SAR ADC,the sampling switch employs the gate-voltage bootstrap structure to improve its nonlinearity;the comparator employs an improved dynamic structure,only one clock is needed and there is no static consumption at all;the successive approximation logic employs a register composed of flip-flops;the residue amplifier uses a self-zeroing structure,and its open-loop DC gain and gain bandwidth product are both large.The sampling switch in the second-stage SAR ADC is a single MOS transistor,and the rest of the structure is similar to the first stage.In the calibration circuit,the capacitor array uses a scheme using low-weight capacitance to calibrate high-weight capacitance,which can theoretically achieve 1LSB accuracy;the comparator uses a calibration scheme of compensating second-stage output load,by which the comparator offset voltage is calibrated to 1/2 LSB in accuracy in a wide range of±25mV;the offset voltage of the residual amplifier is calibrated to the required accuracy by using a discrete-time auto-zeroing scheme.The overall circuit is designed based on TSMC 0.18um CMOS process,and the power consumption is 7.2mW.With the input frequency up to 1.5MHz,the ratio of signal and noise and harmonic wave SNDR of the pre-simulation can reach 98dB or more,and the corresponding effective number of bits ENOB is 16 or more.However,the SNDR of the post-simulation is 90 dB or so,corresponding to ENOB at around 15 bits.